{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:07:09Z","timestamp":1753880829467,"version":"3.41.2"},"reference-count":20,"publisher":"World Scientific Pub Co Pte Ltd","issue":"15","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,10]]},"abstract":"<jats:p> This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator\u2019s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications. <\/jats:p>","DOI":"10.1142\/s0218126622200031","type":"journal-article","created":{"date-parts":[[2022,5,11]],"date-time":"2022-05-11T08:00:29Z","timestamp":1652256029000},"source":"Crossref","is-referenced-by-count":4,"title":["Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT"],"prefix":"10.1142","volume":"31","author":[{"given":"AbdolVahab Khalili","family":"Sadaghiani","sequence":"first","affiliation":[{"name":"Advancom Lab., School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6221-7200","authenticated-orcid":false,"given":"Samad","family":"Sheikhaei","sequence":"additional","affiliation":[{"name":"Advancom Lab., School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"}]},{"given":"Behjat","family":"Forouzandeh","sequence":"additional","affiliation":[{"name":"Advancom Lab., School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"}]}],"member":"219","published-online":{"date-parts":[[2022,6,17]]},"reference":[{"journal-title":"Pattern Anal. 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