{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T09:53:30Z","timestamp":1769248410272,"version":"3.49.0"},"reference-count":23,"publisher":"World Scientific Pub Co Pte Ltd","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,1,15]]},"abstract":"<jats:p> Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395\u2013401], Reviriego et\u00a0al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479\u2013483] and Liu et\u00a0al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92\u201396], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability. <\/jats:p>","DOI":"10.1142\/s0218126622500049","type":"journal-article","created":{"date-parts":[[2021,7,5]],"date-time":"2021-07-05T14:28:38Z","timestamp":1625495318000},"source":"Crossref","is-referenced-by-count":5,"title":["Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory"],"prefix":"10.1142","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1168-1166","authenticated-orcid":false,"given":"Jagannath","family":"Samanta","sequence":"first","affiliation":[{"name":"Department of ECE, Haldia Institute of Technology, Haldia, Purba Medinipur, 721657, West Bengal, India"}]},{"given":"Akash","family":"Kewat","sequence":"additional","affiliation":[{"name":"Department of ECE, Haldia Institute of Technology, Haldia, Purba Medinipur, 721657, West Bengal, India"}]}],"member":"219","published-online":{"date-parts":[[2021,7,3]]},"reference":[{"key":"S0218126622500049BIB001","volume-title":"Error-Control Coding for Computer Systems","author":"Rao T. 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