{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:08:28Z","timestamp":1753884508255,"version":"3.41.2"},"reference-count":29,"publisher":"World Scientific Pub Co Pte Ltd","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,1,15]]},"abstract":"<jats:p> Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC.\u00a0Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator\u2019s propagation delay and decreases its delay variation to 450[Formula: see text]ps. Using TSMC CMOS 130[Formula: see text]nm technology with a sampling frequency of 5.88[Formula: see text]MHz, the simulation result illustrates 788[Formula: see text][Formula: see text]W power consumption with the master clock frequency of 100[Formula: see text]MHz while an integral nonlinearity (INL) of [Formula: see text]1.41\u2013+0.76[Formula: see text]LSB and a differential nonlinearity (DNL) of [Formula: see text]1.05\u2013+0.05[Formula: see text]LSB is achieved in 625[Formula: see text]ps resolution. Finally, figure-of-merit (FoM) depicts 31.2[Formula: see text]fJ\/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications. <\/jats:p>","DOI":"10.1142\/s0218126622500050","type":"journal-article","created":{"date-parts":[[2021,7,16]],"date-time":"2021-07-16T07:06:28Z","timestamp":1626419188000},"source":"Crossref","is-referenced-by-count":0,"title":["An 8-bit Hybrid TDC\/Single-Slope ADC with an Improved Continuous-Time Comparator"],"prefix":"10.1142","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0630-8474","authenticated-orcid":false,"given":"Pedram","family":"Naghieh","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Quchan University of Technology, Mashhad, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ehsan","family":"Rahiminejad","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Quchan University of Technology, Mashhad, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2021,7,15]]},"reference":[{"key":"S0218126622500050BIB001","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea8020012"},{"key":"S0218126622500050BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168872"},{"key":"S0218126622500050BIB003","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2015.1092599"},{"key":"S0218126622500050BIB004","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-019-01534-7"},{"key":"S0218126622500050BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2846592"},{"key":"S0218126622500050BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2662950"},{"key":"S0218126622500050BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2184370"},{"key":"S0218126622500050BIB008","first-page":"75","volume":"2","author":"Sachdeva N.","year":"2011","journal-title":"Int. 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