{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:20:56Z","timestamp":1753881656821,"version":"3.41.2"},"reference-count":19,"publisher":"World Scientific Pub Co Pte Ltd","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,2]]},"abstract":"<jats:p> With advancements in computing and communication technologies on mobile devices, the performance requirements of embedded processors have significantly increased, resulting in a corresponding increase in its energy consumption. Dynamic scaling of operating voltage and operating frequency has a strong correlation to energy minimization in CMOS real-time circuits. Simultaneous optimization of ([Formula: see text], [Formula: see text] pairs under dynamic activity levels is thus extensively investigated over several years. The supply voltage is tuned dynamically during runtime (DVS), with a fixed threshold voltage, to achieve energy minimization. This work addresses the issue of maximizing the energy efficiency of real-time periodic, aperiodic and mixed task sets, in a uniprocessor system, by developing a novel task feasibility methodology, with a novel processor performance-based constraint, to generate the optimal operating supply voltage to the individual task of task sets. The energy minimization of real-time mixed task sets is formulated as Geometric Programming (GP) problem, by varying frequency for periodic tasks sets and keeping fixed frequency for aperiodic tasks set, over a range of task sets and hence computing optimal operating voltages. Simulation experiments show energy savings on the cumulative basis of 50%, 38% and 29% for periodic, aperiodic and mixed task sets, respectively, based on the processing timing constraints of task sets. <\/jats:p>","DOI":"10.1142\/s0218126622500529","type":"journal-article","created":{"date-parts":[[2021,9,24]],"date-time":"2021-09-24T14:13:22Z","timestamp":1632492802000},"source":"Crossref","is-referenced-by-count":1,"title":["A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor System"],"prefix":"10.1142","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5819-2437","authenticated-orcid":false,"given":"H.\u00a0T.","family":"Manohara","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.\u00a0P.","family":"Harish","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering,Bangalore University, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2021,9,23]]},"reference":[{"key":"S0218126622500529BIB001","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2019.01.003"},{"key":"S0218126622500529BIB002","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea1020261"},{"first-page":"1","volume-title":"IEEE Custom Integrated Circuits Conf. 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