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Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V\/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools. <\/jats:p>","DOI":"10.1142\/s0218126622500566","type":"journal-article","created":{"date-parts":[[2021,9,27]],"date-time":"2021-09-27T07:00:40Z","timestamp":1632726040000},"source":"Crossref","is-referenced-by-count":0,"title":["A QFGMOS-Based <i>g<\/i><sub><i>m<\/i><\/sub>-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth"],"prefix":"10.1142","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3309-5515","authenticated-orcid":false,"given":"Urvashi","family":"Bansal","sequence":"first","affiliation":[{"name":"ECE Department, Netaji Subhas University of Technology, New Delhi 110078, India"}]},{"given":"Abhilasha","family":"Bakre","sequence":"additional","affiliation":[{"name":"ECE Department, Netaji Subhas University of Technology, New Delhi 110078, India"}]},{"given":"Prem","family":"Kumar","sequence":"additional","affiliation":[{"name":"ECE Department, Netaji Subhas University of Technology, New Delhi 110078, India"}]},{"given":"Devansh","family":"Yadav","sequence":"additional","affiliation":[{"name":"ECE Department, Netaji Subhas University of Technology, New Delhi 110078, India"}]},{"given":"Mohit","family":"Kumar","sequence":"additional","affiliation":[{"name":"ECE Department, Netaji Subhas University of Technology, New Delhi 110078, India"}]},{"given":"Niranjan","family":"Raj","sequence":"additional","affiliation":[{"name":"ECE Department, Netaji Subhas University of Technology, New Delhi 110078, India"}]}],"member":"219","published-online":{"date-parts":[[2021,9,25]]},"reference":[{"volume-title":"Design of Analog CMOS Integrated Circuits","year":"2001","author":"Razavi B.","key":"S0218126622500566BIB001"},{"doi-asserted-by":"publisher","key":"S0218126622500566BIB002","DOI":"10.1109\/ISCAS.2013.6572221"},{"doi-asserted-by":"publisher","key":"S0218126622500566BIB003","DOI":"10.1049\/el:20020764"},{"doi-asserted-by":"publisher","key":"S0218126622500566BIB004","DOI":"10.1109\/JSSC.1982.1051769"},{"doi-asserted-by":"publisher","key":"S0218126622500566BIB005","DOI":"10.1109\/JSSC.2005.845977"},{"volume-title":"CMOS Analog Circuit Design","year":"2002","author":"Allen P. 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