{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:14:56Z","timestamp":1753884896249,"version":"3.41.2"},"reference-count":26,"publisher":"World Scientific Pub Co Pte Ltd","issue":"04","funder":[{"DOI":"10.13039\/501100001412","name":"Council of Scientific and Industrial Research","doi-asserted-by":"crossref","award":["09\/677(0036)\/2018-EMR-I"],"award-info":[{"award-number":["09\/677(0036)\/2018-EMR-I"]}],"id":[{"id":"10.13039\/501100001412","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,3,15]]},"abstract":"<jats:p> This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180[Formula: see text]nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1[Formula: see text]V to 1.8[Formula: see text]V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed &amp; auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8[Formula: see text]V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55[Formula: see text]mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is [Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. <\/jats:p>","DOI":"10.1142\/s0218126622500591","type":"journal-article","created":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T08:18:32Z","timestamp":1633940312000},"source":"Crossref","is-referenced-by-count":0,"title":["A Scalable Fully-Digital Differential Analog Voltage Comparator"],"prefix":"10.1142","volume":"31","author":[{"given":"Ashima","family":"Gupta","sequence":"first","affiliation":[{"name":"Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8087-1708","authenticated-orcid":false,"given":"Anil","family":"Singh","sequence":"additional","affiliation":[{"name":"Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]},{"given":"Alpana","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology, Patiala, Punjab, India"}]}],"member":"219","published-online":{"date-parts":[[2021,10,9]]},"reference":[{"key":"S0218126622500591BIB001","first-page":"3107","volume":"60","author":"Crovetti P. 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