{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:09:06Z","timestamp":1753884546692,"version":"3.41.2"},"reference-count":23,"publisher":"World Scientific Pub Co Pte Ltd","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,5,15]]},"abstract":"<jats:p> In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm\/<jats:sup>\u2218<\/jats:sup>C across [Formula: see text]C to 85<jats:sup>\u2218<\/jats:sup>C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%\/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]\/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch. <\/jats:p>","DOI":"10.1142\/s0218126622501195","type":"journal-article","created":{"date-parts":[[2021,12,21]],"date-time":"2021-12-21T16:46:39Z","timestamp":1640105199000},"source":"Crossref","is-referenced-by-count":2,"title":["3.48-nW 58.4ppm\/\u00b0C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors"],"prefix":"10.1142","volume":"31","author":[{"given":"Mohammadreza","family":"Rasekhi","sequence":"first","affiliation":[{"name":"IC Design Research Lab, Department of Electrical Engineering, Shahrood University of Technology, Shahrood 3619995161, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emad","family":"Ebrahimi","sequence":"additional","affiliation":[{"name":"IC Design Research Lab, Department of Electrical Engineering, Shahrood University of Technology, Shahrood 3619995161, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamed","family":"Aminzadeh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Payame Noor University (PNU), Tehran 19395-4697, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2021,12,20]]},"reference":[{"key":"S0218126622501195BIB001","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-009-9352-4"},{"key":"S0218126622501195BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2577978"},{"key":"S0218126622501195BIB003","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-020-01660-7"},{"key":"S0218126622501195BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/4.760378"},{"key":"S0218126622501195BIB005","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126621500298"},{"key":"S0218126622501195BIB006","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.1761"},{"key":"S0218126622501195BIB007","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2510"},{"key":"S0218126622501195BIB008","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2383"},{"key":"S0218126622501195BIB009","doi-asserted-by":"publisher","DOI":"10.1049\/el.2012.0857"},{"key":"S0218126622501195BIB010","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126619501202"},{"key":"S0218126622501195BIB011","doi-asserted-by":"publisher","DOI":"10.1049\/el:20050316"},{"key":"S0218126622501195BIB012","doi-asserted-by":"publisher","DOI":"10.1049\/el.2019.3671"},{"key":"S0218126622501195BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2920693"},{"key":"S0218126622501195BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2794512"},{"key":"S0218126622501195BIB015","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2020.104841"},{"key":"S0218126622501195BIB016","doi-asserted-by":"publisher","DOI":"10.1002\/9780470033715"},{"key":"S0218126622501195BIB017","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea6020010"},{"key":"S0218126622501195BIB019","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2092997"},{"key":"S0218126622501195BIB020","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.0193"},{"key":"S0218126622501195BIB022","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2020.153245"},{"key":"S0218126622501195BIB023","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2602875"},{"key":"S0218126622501195BIB024","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2252523"},{"key":"S0218126622501195BIB025","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2857626"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126622501195","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,22]],"date-time":"2022-04-22T11:23:07Z","timestamp":1650626587000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126622501195"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,20]]},"references-count":23,"journal-issue":{"issue":"07","published-print":{"date-parts":[[2022,5,15]]}},"alternative-id":["10.1142\/S0218126622501195"],"URL":"https:\/\/doi.org\/10.1142\/s0218126622501195","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2021,12,20]]},"article-number":"2250119"}}