{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,6]],"date-time":"2026-02-06T02:07:06Z","timestamp":1770343626012,"version":"3.49.0"},"reference-count":17,"publisher":"World Scientific Pub Co Pte Ltd","issue":"09","funder":[{"DOI":"10.13039\/501100008628","name":"ministry of electronics and information technology","doi-asserted-by":"publisher","award":["VISPHD-MEITY-1864"],"award-info":[{"award-number":["VISPHD-MEITY-1864"]}],"id":[{"id":"10.13039\/501100008628","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,6]]},"abstract":"<jats:p> Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512[Formula: see text]mW of power with an ENOB of 7.56 bits and SNDR of 46.27[Formula: see text]dB for 1[Formula: see text]GHz sampling clock pulse. <\/jats:p>","DOI":"10.1142\/s0218126622501699","type":"journal-article","created":{"date-parts":[[2022,2,14]],"date-time":"2022-02-14T15:31:27Z","timestamp":1644852687000},"source":"Crossref","is-referenced-by-count":1,"title":["Resolution-Selective and Resolution-Adaptive 2 to 8-Bit Flash ADC for High-Speed Application-Independent IC (HS-AIIC)"],"prefix":"10.1142","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2585-1122","authenticated-orcid":false,"given":"Sarfraz","family":"Hussain","sequence":"first","affiliation":[{"name":"ECE Department, MITS, Madanapalle, Andhra Pradesh 517325, India"}]}],"member":"219","published-online":{"date-parts":[[2022,3,24]]},"reference":[{"key":"S0218126622501699BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658753"},{"key":"S0218126622501699BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2010.5716609"},{"key":"S0218126622501699BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2011.6123645"},{"key":"S0218126622501699BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2241799"},{"key":"S0218126622501699BIB005","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.3272"},{"key":"S0218126622501699BIB006","first-page":"II-87","volume-title":"The 2002 45th Midwest Symp. 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