{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T05:16:13Z","timestamp":1774934173412,"version":"3.50.1"},"reference-count":31,"publisher":"World Scientific Pub Co Pte Ltd","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,7,30]]},"abstract":"<jats:p> Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from [Formula: see text] to [Formula: see text] are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is [Formula: see text] to [Formula: see text] with respect to BookSim simulator. <\/jats:p>","DOI":"10.1142\/s0218126622501961","type":"journal-article","created":{"date-parts":[[2022,4,30]],"date-time":"2022-04-30T02:00:41Z","timestamp":1651284041000},"source":"Crossref","is-referenced-by-count":3,"title":["LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures"],"prefix":"10.1142","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7288-7697","authenticated-orcid":false,"given":"Anil","family":"Kumar","sequence":"first","affiliation":[{"name":"Systems, Parallelization and Architecture Research Lab (SPARK-Lab), Department of Computer Science and Engineering, National Institute of Technology Karnataka Surathkal, Mangalore 575 025, Karnataka, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Basavaraj","family":"Talawar","sequence":"additional","affiliation":[{"name":"Systems, Parallelization and Architecture Research Lab (SPARK-Lab), Department of Computer Science and Engineering, National Institute of Technology Karnataka Surathkal, Mangalore 575 025, Karnataka, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2022,4,29]]},"reference":[{"key":"S0218126622501961BIB001","first-page":"684","volume-title":"Proc. 38th Annual Design Automation Conf.","author":"Dally W. J.","year":"2001"},{"key":"S0218126622501961BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"S0218126622501961BIB003","first-page":"11","volume-title":"Proc. IEEE NorChip Conf.","volume":"31","author":"Hemani A.","year":"2000"},{"key":"S0218126622501961BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"S0218126622501961BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2015.7245728"},{"key":"S0218126622501961BIB006","first-page":"16","volume-title":"Design, Automation and Test in Europe Conf.","author":"Jain L.","year":"2007"},{"key":"S0218126622501961BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2002.994207"},{"key":"S0218126622501961BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091686"},{"key":"S0218126622501961BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"S0218126622501961BIB010","first-page":"1","volume":"9","author":"Angepat H.","year":"2014","journal-title":"Synth. Lect. Comput. Arch."},{"key":"S0218126622501961BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2011.164"},{"key":"S0218126622501961BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.10"},{"key":"S0218126622501961BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/NESEA.2011.6144949"},{"key":"S0218126622501961BIB014","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.083"},{"key":"S0218126622501961BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474393"},{"key":"S0218126622501961BIB016","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419887"},{"key":"S0218126622501961BIB017","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2010.2051413"},{"key":"S0218126622501961BIB018","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742078"},{"key":"S0218126622501961BIB019","doi-asserted-by":"publisher","DOI":"10.1109\/NoCS.2013.6558418"},{"key":"S0218126622501961BIB020","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2401013"},{"key":"S0218126622501961BIB021","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927203"},{"key":"S0218126622501961BIB022","volume-title":"Proc. IEEE 1st Int. Workshop AI-Assisted Design Architecture","author":"Yin J.","year":"2018"},{"key":"S0218126622501961BIB023","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2012.6404180"},{"key":"S0218126622501961BIB024","doi-asserted-by":"publisher","DOI":"10.1109\/IC3.2018.8530505"},{"key":"S0218126622501961BIB027","doi-asserted-by":"publisher","DOI":"10.1023\/B:STCO.0000035301.49549.88"},{"key":"S0218126622501961BIB028","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijrmms.2014.09.012"},{"key":"S0218126622501961BIB029","doi-asserted-by":"publisher","DOI":"10.1023\/A:1009715923555"},{"key":"S0218126622501961BIB030","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-6849-3"},{"key":"S0218126622501961BIB031","first-page":"230","volume-title":"Advances in Neural Information Processing Systems","author":"Chapelle O.","year":"2000"},{"key":"S0218126622501961BIB032","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4471-1599-1_12"},{"key":"S0218126622501961BIB033","doi-asserted-by":"publisher","DOI":"10.1162\/089976600300015565"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126622501961","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,25]],"date-time":"2022-07-25T07:31:35Z","timestamp":1658734295000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126622501961"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,29]]},"references-count":31,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2022,7,30]]}},"alternative-id":["10.1142\/S0218126622501961"],"URL":"https:\/\/doi.org\/10.1142\/s0218126622501961","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,4,29]]},"article-number":"2250196"}}