{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:03:24Z","timestamp":1753884204628,"version":"3.41.2"},"reference-count":21,"publisher":"World Scientific Pub Co Pte Ltd","issue":"16","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2022,11,15]]},"abstract":"<jats:p> A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0[Formula: see text]A) to 10 or 30[Formula: see text]A or else 50[Formula: see text]A in 10[Formula: see text]ns. Simulated in a 0.09-[Formula: see text]m CMOS process and power supply voltage ([Formula: see text]) of 1.1[Formula: see text]V, the proposed circuit in post-layout can operate from 435.5[Formula: see text]ps to 152.2[Formula: see text]ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5[Formula: see text]ps for NN and SS process corner, respectively, following a [Formula: see text]C change in temperature. But an abrupt high current [Formula: see text] pumped into the chip causes the voltage ([Formula: see text]) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp [Formula: see text] of 0\u201350[Formula: see text]A in 10[Formula: see text]ns for the two vector CBA happens to be around 5.0 and 4.4[Formula: see text]ps, respectively. The current ramp also generates power supply noise of 0.468[Formula: see text]V occurring close to the silicon chip. This, in turn, corresponds to a [Formula: see text] of 0.642[Formula: see text]V near the die, appearing to be much less than the required [Formula: see text] of 1.1[Formula: see text]V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642[Formula: see text]V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage. <\/jats:p>","DOI":"10.1142\/s0218126622502760","type":"journal-article","created":{"date-parts":[[2022,5,23]],"date-time":"2022-05-23T02:37:37Z","timestamp":1653273457000},"source":"Crossref","is-referenced-by-count":1,"title":["Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current"],"prefix":"10.1142","volume":"31","author":[{"given":"Mithilesh","family":"Kumar","sequence":"first","affiliation":[{"name":"Department of Electronics & Communication Engineering, NIT Arunachal Pradesh, Jote, Arunachal Pradesh 791113, India"}]},{"given":"Alak","family":"Majumder","sequence":"additional","affiliation":[{"name":"Department of Electronics & Communication Engineering, NIT Arunachal Pradesh, Jote, Arunachal Pradesh 791113, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8023-4103","authenticated-orcid":false,"given":"Abir J","family":"Mondal","sequence":"additional","affiliation":[{"name":"Department of Electronics & Communication Engineering, NIT Arunachal Pradesh, Jote, Arunachal Pradesh 791113, India"}]}],"member":"219","published-online":{"date-parts":[[2022,6,24]]},"reference":[{"key":"S0218126622502760BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2820181"},{"key":"S0218126622502760BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2082272"},{"key":"S0218126622502760BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2313131"},{"key":"S0218126622502760BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/4.826820"},{"first-page":"2653","volume-title":"IEEE Int. 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