{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:10:46Z","timestamp":1753884646178,"version":"3.41.2"},"reference-count":41,"publisher":"World Scientific Pub Co Pte Ltd","issue":"03","funder":[{"name":"Ministry of Electronics and Information Technology (MeitY), Government of India","award":["SMDP-C2SD"],"award-info":[{"award-number":["SMDP-C2SD"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,2]]},"abstract":"<jats:p> High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process. <\/jats:p>","DOI":"10.1142\/s0218126623500408","type":"journal-article","created":{"date-parts":[[2022,8,12]],"date-time":"2022-08-12T04:54:20Z","timestamp":1660280060000},"source":"Crossref","is-referenced-by-count":0,"title":["Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL"],"prefix":"10.1142","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3540-9546","authenticated-orcid":false,"given":"Priti","family":"Gupta","sequence":"first","affiliation":[{"name":"Electronics and Communication Engineering Department, NIT Sikkim, Ravangla, Sikkim 737139, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay Kumar","family":"Jana","sequence":"additional","affiliation":[{"name":"Electronics and Communication Engineering Department, NIT Sikkim, Ravangla, Sikkim 737139, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2022,9,14]]},"reference":[{"key":"S0218126623500408BIB001","doi-asserted-by":"crossref","first-page":"1137","DOI":"10.1109\/4.859502","volume":"35","author":"Lo Y.","year":"2000","journal-title":"IEEE J. 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