{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:19:18Z","timestamp":1753881558225,"version":"3.41.2"},"reference-count":26,"publisher":"World Scientific Pub Co Pte Ltd","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,2]]},"abstract":"<jats:p> Frequency-modulated continuous-wave (FMCW) signals-based radar systems can outrun the optical and ultrasound sensors in dark and severe weather conditions. FMCW radar systems require a fast settling frequency synthesizer to reduce the chirp signal\u2019s inactive and modulation times. This work proposes a new C-B and FMCW Transmitter based on Fast Settling Fractional-N DPLL (FS-FNDPLL) and ring-based pulse injection locking oscillator (R-PILO). The proposed FS-FNDPLL generates an ultra-fast low-noise smooth narrowband chirp by introducing an automatic controller-based TDC switching (AC-TDCSw) scheme in the forward loop of FNDPLL. Also, the proposed FS-FNDPLL employs a new background gain calibrated digital-to-time converter (BGC-DTC) as a fractional divider in the feedback path for the quantization noise cancellation (QNC). The proposed FMCW transmitter uses an R-PILO to produce fast switching adjacent carriers after generating a narrowband chirp using FS-FNDPLL. The main features of the proposed FMCW to accelerate settling time with AC-TDCSw, BGC-DTC and the integration of spur suppressing pulse generator (SSPG) in R-PILO enable ultra-fast chirps with less phase noise and spur levels. The proposed transmitter up-converts the 500[Formula: see text]MHz narrowband chirp signal onto four adjacent carriers for obtaining a 2[Formula: see text]GHz chirp at the C-band. The simulation results prove that the proposed FMCW Transmitter consumes 79[Formula: see text]mW power. Furthermore, the phase noise of the proposed FS-FNDPLL is reduced to [Formula: see text][Formula: see text]dBc\/Hz at 1[Formula: see text]MHz. The proposed FS-FNDPLL reduces the settling time to 1[Formula: see text][Formula: see text]s with the introduced AC-TDCSw scheme. <\/jats:p>","DOI":"10.1142\/s0218126623500457","type":"journal-article","created":{"date-parts":[[2022,8,12]],"date-time":"2022-08-12T04:52:25Z","timestamp":1660279945000},"source":"Crossref","is-referenced-by-count":1,"title":["An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator"],"prefix":"10.1142","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2340-998X","authenticated-orcid":false,"given":"Abdul","family":"Muqueem","sequence":"first","affiliation":[{"name":"VLSI Design, School of Electronics & Electrical Engineering, Lovely Professional University, Punjab 144411, India"}]},{"given":"Shanky","family":"Saxena","sequence":"additional","affiliation":[{"name":"VLSI Design, School of Electronics & Electrical Engineering, Lovely Professional University, Punjab 144411, India"}]},{"given":"Govind Singh","family":"Patel","sequence":"additional","affiliation":[{"name":"Electronics and Computer Engineering, SITCOE, Yadrav, Kolhapur, Maharashtra, India"}]}],"member":"219","published-online":{"date-parts":[[2022,9,16]]},"reference":[{"key":"S0218126623500457BIB001","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1109\/MMM.2015.2393995","volume":"16","author":"Munoz-Ferreras J. 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