{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:36:57Z","timestamp":1753882617067,"version":"3.41.2"},"reference-count":24,"publisher":"World Scientific Pub Co Pte Ltd","issue":"04","funder":[{"DOI":"10.13039\/501100002183","name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology","doi-asserted-by":"publisher","award":["9(1)\/2014-MDD"],"award-info":[{"award-number":["9(1)\/2014-MDD"]}],"id":[{"id":"10.13039\/501100002183","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,3,15]]},"abstract":"<jats:p> Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply. <\/jats:p>","DOI":"10.1142\/s0218126623500597","type":"journal-article","created":{"date-parts":[[2022,8,24]],"date-time":"2022-08-24T08:52:09Z","timestamp":1661331129000},"source":"Crossref","is-referenced-by-count":2,"title":["A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency"],"prefix":"10.1142","volume":"32","author":[{"given":"Ravi","family":"Kumar","sequence":"first","affiliation":[{"name":"NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, M.P. 453552, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajasekhar","family":"Nagulapalli","sequence":"additional","affiliation":[{"name":"School of Engineering, Computing, and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4223-0077","authenticated-orcid":false,"given":"Santosh Kumar","family":"Vishvakarma","sequence":"additional","affiliation":[{"name":"NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, M.P. 453552, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2022,9,28]]},"reference":[{"key":"S0218126623500597BIB001","doi-asserted-by":"crossref","first-page":"860","DOI":"10.1109\/TCSII.2003.819120","volume":"50","author":"Kim J.","year":"2003","journal-title":"IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process."},{"key":"S0218126623500597BIB002","doi-asserted-by":"crossref","first-page":"569","DOI":"10.1109\/VLSI.Design.2009.97","volume-title":"2009 22nd Int. Conf. VLSI Design","author":"Easwaran P.","year":"2009"},{"key":"S0218126623500597BIB003","doi-asserted-by":"crossref","first-page":"267","DOI":"10.1109\/ISVLSI.2014.15","volume-title":"2014 IEEE Computer Society Annual Symp. VLSI","author":"Wang Y.","year":"2014"},{"key":"S0218126623500597BIB004","first-page":"569","volume-title":"Proc. IEEE Int. Symp. Circuits Systems","author":"Chen H.","year":"1999"},{"key":"S0218126623500597BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2009.2017246"},{"key":"S0218126623500597BIB006","doi-asserted-by":"crossref","first-page":"1850186","DOI":"10.1142\/S0218126618501864","volume":"27","author":"Zied S.","year":"2018","journal-title":"J. Circuits, Syst. Comput."},{"key":"S0218126623500597BIB007","doi-asserted-by":"crossref","first-page":"2312","DOI":"10.1109\/JSSC.2016.2581815","volume":"51","author":"Jeong G.-S.","year":"2016","journal-title":"IEEE J. Solid-State Circuits"},{"key":"S0218126623500597BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/16.75219"},{"key":"S0218126623500597BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCT.2017.8117953"},{"key":"S0218126623500597BIB010","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1007\/s10470-012-9993-6","volume":"74","author":"Vijayaraghavan R.","year":"2013","journal-title":"Analog Integr. Circuits Signal Process."},{"key":"S0218126623500597BIB011","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1049\/iet-cds.2008.0362","volume":"3","author":"Vijayaraghavan R.","year":"2009","journal-title":"IET Circuits Dev. Syst."},{"key":"S0218126623500597BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/ICMDCS.2017.8211722"},{"key":"S0218126623500597BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617407"},{"edition":"2","volume-title":"Design of Analog CMOS Integrated Circuits","author":"Razavi B.","key":"S0218126623500597BIB014"},{"key":"S0218126623500597BIB015","doi-asserted-by":"crossref","first-page":"2050128","DOI":"10.1142\/S0218126620501285","volume":"29","author":"Sakka Z.","year":"2020","journal-title":"J. Circuits Syst. Comput."},{"key":"S0218126623500597BIB016","first-page":"389","volume":"56","author":"Lakshmikumar K. R.","year":"2009","journal-title":"IEEE Trans. Circuits Syst. II, Express Briefs"},{"key":"S0218126623500597BIB017","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1007\/s00034-022-02001-x","volume":"41","author":"Kandpal N.","year":"2022","journal-title":"Circuits Syst. Signal Process."},{"key":"S0218126623500597BIB018","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8101156"},{"key":"S0218126623500597BIB019","doi-asserted-by":"crossref","first-page":"1115","DOI":"10.1109\/TCSI.2021.3123279","volume":"69","author":"Shahghasemi M.","year":"2022","journal-title":"IEEE Trans. Circuits Syst. I, Regul. Papers"},{"key":"S0218126623500597BIB020","doi-asserted-by":"crossref","first-page":"722","DOI":"10.1109\/ASICON.2017.8252577","volume-title":"2017 IEEE 12th Int. Conf. ASIC (ASICON)","author":"Gao Y.","year":"2017"},{"key":"S0218126623500597BIB021","first-page":"1","volume-title":"East-West Design & Test Symp.","author":"Melikyan V.","year":"2013"},{"key":"S0218126623500597BIB022","first-page":"190","volume-title":"2020 11th Int. Conf. Electrical and Computer Engineering (ICECE)","author":"Ahsan S. M. M.","year":"2020"},{"key":"S0218126623500597BIB023","first-page":"1","volume-title":"2017 IEEE Int. Symp. Circuits and Systems (ISCAS)","author":"Zhang Y.","year":"2017"},{"key":"S0218126623500597BIB024","doi-asserted-by":"crossref","first-page":"260","DOI":"10.1109\/ISSCC.2019.8662312","volume-title":"2019 IEEE Int. Solid- State Circuits Conf. (ISSCC)","author":"Yang X.","year":"2019"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126623500597","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,24]],"date-time":"2023-02-24T03:14:30Z","timestamp":1677208470000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126623500597"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,9,28]]},"references-count":24,"journal-issue":{"issue":"04","published-print":{"date-parts":[[2023,3,15]]}},"alternative-id":["10.1142\/S0218126623500597"],"URL":"https:\/\/doi.org\/10.1142\/s0218126623500597","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2022,9,28]]},"article-number":"2350059"}}