{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T12:33:10Z","timestamp":1764333190642,"version":"3.41.2"},"reference-count":30,"publisher":"World Scientific Pub Co Pte Ltd","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,5,15]]},"abstract":"<jats:p> Due to technological advancements and voltage scaling, leakage power has become an important concern in CMOS design. The implementation of a field-programmable gate array (FPGA) circuit utilizes a portion of the FPGA\u2019s resources as compared to an application-specific integrated circuit (ASIC). Both the utilized and unutilized parts of the FPGA dissipate leakage power. In this work, two dynamic power gating techniques, PSG-1 and PSG-2, are proposed, which are able to reduce the leakage power of the 6-input look-up table (LUT) used in the Xilinx Spartan-6 series. The obtained results show that the proposed approaches PSG-1 and PSG-2 reduce average leakage power by 54.61% and 66.69%, respectively, at the expense of nominal area and delay overhead. The proposed method is also capable of lowering the average total power of the 6-input LUT. The suggested PSG-1 and PSG-2 approaches reduce average power by 53.75% and 60.83%, respectively. However, header-based power supply gating is extremely vulnerable to the negative-bias temperature instability (NBTI) aging effect and, due to this, the lifetime of the circuit is reduced considerably. Therefore, in this work, lifetime estimation-based analysis is performed by varying the stress probability of the sleep transistor. The results show that the LUT with PSG-1 and PSG-2 techniques has a lifetime of 4.55 years and 11.13 years, respectively. The stress time of the sleep transistor is 50% for the PSG-1 technique and 25% for the PSG-2 technique, respectively. <\/jats:p>","DOI":"10.1142\/s021812662350113x","type":"journal-article","created":{"date-parts":[[2022,10,7]],"date-time":"2022-10-07T17:38:56Z","timestamp":1665164336000},"source":"Crossref","is-referenced-by-count":3,"title":["Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA"],"prefix":"10.1142","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4614-7633","authenticated-orcid":false,"given":"Vivek Kumar","family":"Singh","sequence":"first","affiliation":[{"name":"Department of ECE, National Institute of Technology, Agartala, Agartala, Tripura 799046, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhishek","family":"Nag","sequence":"additional","affiliation":[{"name":"Department of ECE, National Institute of Technology, Agartala, Agartala, Tripura 799046, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhishek","family":"Bhattacharjee","sequence":"additional","affiliation":[{"name":"Department of ECE, National Institute of Technology, Agartala, Agartala, Tripura 799046, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sambhu Nath","family":"Pradhan","sequence":"additional","affiliation":[{"name":"Department of ECE, National Institute of Technology, Agartala, Agartala, Tripura 799046, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2022,11,24]]},"reference":[{"key":"S021812662350113XBIB001","doi-asserted-by":"crossref","first-page":"191","DOI":"10.1109\/92.766746","volume":"7","author":"Chow P.","year":"1999","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"S021812662350113XBIB002","doi-asserted-by":"crossref","first-page":"597","DOI":"10.4103\/0377-2063.123766","volume":"59","author":"Jahanirad H.","year":"2013","journal-title":"IETE J. Res."},{"key":"S021812662350113XBIB003","first-page":"1029","volume":"38","author":"Verma G.","year":"2017","journal-title":"J. Inf. Optimiz. Sci."},{"key":"S021812662350113XBIB004","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1109\/TCAD.2005.853692","volume":"25","author":"Anderson J. H.","year":"2006","journal-title":"IEEE Trans. Comput.-aided Des. Integr. Circuits Syst."},{"key":"S021812662350113XBIB005","first-page":"1","volume":"298","author":"Klein M.","year":"2009","journal-title":"White Paper"},{"key":"S021812662350113XBIB006","doi-asserted-by":"crossref","first-page":"1394","DOI":"10.1109\/TVLSI.2010.2050500","volume":"19","author":"Ishihara S.","year":"2010","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"S021812662350113XBIB007","first-page":"259","volume-title":"Advances in Computers","volume":"110","author":"Seifoori Z.","year":"2018"},{"key":"S021812662350113XBIB008","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1109\/TVLSI.2015.2393914","volume":"24","author":"Bsoul A. A.","year":"2016","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"first-page":"1","volume-title":"2010 International Conference on Field-Programmable Technology","author":"Bsoul A. A.","key":"S021812662350113XBIB009"},{"key":"S021812662350113XBIB010","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/ICFPT47387.2019.00010","volume-title":"2019 Int. Conf. Field-Programmable Technology (ICFPT)","author":"Seifoori Z.","year":"2019"},{"key":"S021812662350113XBIB011","first-page":"1342","volume-title":"Design, Automation & Test in Europe Conf. & Exhibition (DATE)","author":"Seifoori Z.","year":"2017"},{"key":"S021812662350113XBIB012","doi-asserted-by":"crossref","first-page":"1750041","DOI":"10.1142\/S0218126617500414","volume":"26","author":"Nag A.","year":"2017","journal-title":"J. Circuits, Syst. Comput."},{"key":"S021812662350113XBIB013","first-page":"1","volume-title":"2014 24th Int. Conf. Field Programmable Logic and Applications (FPL)","author":"Hosseinabady M.","year":"2014"},{"key":"S021812662350113XBIB014","doi-asserted-by":"crossref","first-page":"1163","DOI":"10.1016\/j.proeng.2012.01.976","volume":"30","author":"Priya M. G.","year":"2012","journal-title":"Proc. Eng."},{"key":"S021812662350113XBIB015","first-page":"42","volume":"55","author":"Saini P.","year":"2012","journal-title":"Int. J. Comput. Appl."},{"key":"S021812662350113XBIB016","first-page":"187","volume-title":"Proc. IEEE 2005 Custom Integrated Circuits Conf.","author":"Azizi N.","year":"2005"},{"key":"S021812662350113XBIB017","first-page":"2052","volume-title":"Proc. 2006 8th Int. Conf. Solid-State and Integrated Circuit Technology","author":"Yang S.","year":"2006"},{"key":"S021812662350113XBIB019","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126617501778"},{"key":"S021812662350113XBIB020","first-page":"249","volume":"59","author":"Calimera A.","year":"2012","journal-title":"IEEE Trans. Circuits Syst. II, Express Briefs"},{"key":"S021812662350113XBIB021","doi-asserted-by":"crossref","DOI":"10.1142\/S0218126621200048","volume":"30","author":"Bhattacharjee A.","year":"2021","journal-title":"J. Circuits Syst. Comput."},{"key":"S021812662350113XBIB022","doi-asserted-by":"crossref","first-page":"2735","DOI":"10.1109\/TVLSI.2016.2519385","volume":"24","author":"Rossi D.","year":"2016","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"S021812662350113XBIB023","doi-asserted-by":"crossref","first-page":"361","DOI":"10.1049\/iet-cds:20070225","volume":"2","author":"Bhardwaj S.","year":"2008","journal-title":"IET Circuits Dev. Syst."},{"key":"S021812662350113XBIB024","doi-asserted-by":"crossref","first-page":"559","DOI":"10.1109\/ICCD.2005.34","volume-title":"2005 Int. Conf. Computer Design","author":"Jiang H.","year":"2005"},{"key":"S021812662350113XBIB025","doi-asserted-by":"crossref","first-page":"651","DOI":"10.1109\/TVLSI.2018.2886326","volume":"27","author":"Khaleghi B.","year":"2019","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"S021812662350113XBIB026","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1109\/TDSC.2007.70235","volume":"5","author":"Srinivasan S.","year":"2008","journal-title":"IEEE Trans. Depend. Secure Comput."},{"key":"S021812662350113XBIB027","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1109\/TDMR.2020.2974131","volume":"20","author":"Dankovi D.","year":"2020","journal-title":"IEEE Trans. Dev. Mater. Reliabil."},{"key":"S021812662350113XBIB028","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/TDMR.2020.2967696","volume":"20","author":"Mahapatra S.","year":"2020","journal-title":"IEEE Trans. Dev. Mater. Reliabil."},{"issue":"1","key":"S021812662350113XBIB029","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1007\/s10836-022-05990-4","volume":"38","author":"Bhattacharjee A.","year":"2022","journal-title":"J. Electron. Test."},{"key":"S021812662350113XBIB030","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1016\/j.microrel.2018.01.003","volume":"82","author":"Dankovi D.","year":"2018","journal-title":"Microelectron. Reliab."},{"key":"S021812662350113XBIB031","doi-asserted-by":"crossref","first-page":"1828","DOI":"10.1016\/j.microrel.2006.07.077","volume":"46","author":"Dankovi D.","year":"2006","journal-title":"Microelectron. Reliab."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S021812662350113X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,21]],"date-time":"2023-05-21T03:35:49Z","timestamp":1684640149000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S021812662350113X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,24]]},"references-count":30,"journal-issue":{"issue":"07","published-print":{"date-parts":[[2023,5,15]]}},"alternative-id":["10.1142\/S021812662350113X"],"URL":"https:\/\/doi.org\/10.1142\/s021812662350113x","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2022,11,24]]},"article-number":"2350113"}}