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Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy. <\/jats:p>","DOI":"10.1142\/s0218126623501487","type":"journal-article","created":{"date-parts":[[2022,11,14]],"date-time":"2022-11-14T07:46:56Z","timestamp":1668412016000},"source":"Crossref","is-referenced-by-count":6,"title":["Design and Implementation of a Sense Amplifier for Low-Power Cardiac Pacemaker"],"prefix":"10.1142","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6830-0742","authenticated-orcid":false,"given":"Pavankumar","family":"Bikki","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication, B V Raju Institute of Technology, Narsapur, Telangana, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yenduri","family":"Dhiraj","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication, National Institute of Technology Andhra Pradesh, Tadepalligudem, Andhra Pradesh, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"R. 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