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The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source ([Formula: see text]) capacitance of the main transistor is compensated by the linearizer. Thus, it improves the 3rd-order intermodulation point (OIP3) without trading-off the power added efficiency (PAE). The proposed solution is designed and fabricated in an 180[Formula: see text]nm CMOS technology process consuming the chip area of 2.25[Formula: see text]mm<jats:sup>2<\/jats:sup>. At the operating frequency of 2.45[Formula: see text]GHz, it exhibits a gain of 11.14[Formula: see text]dB with unconditional stability characteristics from 1[Formula: see text]GHz to 10[Formula: see text]GHz. Biased quiescent current of 19.35[Formula: see text]mA, the IPL-PA delivers a maximum output power of 15.20[Formula: see text]dBm with 40.86% peak PAE, 34.91[Formula: see text]dBm of peak OIP3 and maximum power consumption of 63.65[Formula: see text]mW at 2.45[Formula: see text]GHz with supply voltage headroom of 1.8[Formula: see text]V. The proposed linearization scheme proved to be an excellent solution for low-power transceivers integration. <\/jats:p>","DOI":"10.1142\/s021812662350189x","type":"journal-article","created":{"date-parts":[[2022,12,9]],"date-time":"2022-12-09T03:23:18Z","timestamp":1670556198000},"source":"Crossref","is-referenced-by-count":0,"title":["A 40% PAE and 34 dBm Peak OIP3 CMOS Power Amplifier with Integrated Zero Power Consumption Phase Linearizer"],"prefix":"10.1142","volume":"32","author":[{"given":"Premmilaah","family":"Gunasegaran","sequence":"first","affiliation":[{"name":"Collaborative Microelectronic Design Excellence Centre (CEDEC) Engineering Campus, Universiti Sains Malaysia, 11900 Georgetown, Penang, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0313-8462","authenticated-orcid":false,"given":"Jagadheswaran","family":"Rajendran","sequence":"additional","affiliation":[{"name":"Collaborative Microelectronic Design Excellence Centre (CEDEC) Engineering Campus, Universiti Sains Malaysia, 11900 Georgetown, Penang, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Selvakumar","family":"Mariappan","sequence":"additional","affiliation":[{"name":"Collaborative Microelectronic Design Excellence Centre (CEDEC) Engineering Campus, Universiti Sains Malaysia, 11900 Georgetown, Penang, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusman","family":"Yusof","sequence":"additional","affiliation":[{"name":"SilTerra Malaysia Sdn Bhd, 09000 Kulim, Kedah, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zulfiqar Ali Abd","family":"Aziz","sequence":"additional","affiliation":[{"name":"Collaborative Microelectronic Design Excellence Centre (CEDEC) Engineering Campus, Universiti Sains Malaysia, 11900 Georgetown, Penang, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Narendra","family":"Kumar","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2023,1,11]]},"reference":[{"key":"S021812662350189XBIB001","first-page":"901","volume":"56","author":"Boo H. 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