{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:12:04Z","timestamp":1753884724013,"version":"3.41.2"},"reference-count":22,"publisher":"World Scientific Pub Co Pte Ltd","issue":"13","funder":[{"DOI":"10.13039\/501100011688","name":"ECSEL Joint Undertaking","doi-asserted-by":"crossref","award":["876124"],"award-info":[{"award-number":["876124"]}],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,9,15]]},"abstract":"<jats:p> In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than \u221288[Formula: see text]dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to \u221255[Formula: see text]dBc. Using the loop sampling technique provides a spur reduction of 33[Formula: see text]dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of \u221297\/\u221299\/\u2212114[Formula: see text]dBc for 10[Formula: see text]kHz\/100[Formula: see text]kHz\/1[Formula: see text]MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6[Formula: see text]mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18[Formula: see text]mW. <\/jats:p>","DOI":"10.1142\/s0218126623502237","type":"journal-article","created":{"date-parts":[[2023,1,25]],"date-time":"2023-01-25T12:54:14Z","timestamp":1674651254000},"source":"Crossref","is-referenced-by-count":1,"title":["A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications"],"prefix":"10.1142","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2963-5395","authenticated-orcid":false,"given":"Emre","family":"Ulusoy","sequence":"first","affiliation":[{"name":"T\u00dcB\u0130TAK\u2014Informatics and Information Security Research Center, 41470 Gebze, Kocaeli, Turkey"},{"name":"Department of Electronics Engineering, Istanbul Technical University, 34467 Maslak, Istanbul, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ertan","family":"Zencir","sequence":"additional","affiliation":[{"name":"T\u00dcB\u0130TAK\u2014Informatics and Information Security Research Center, 41470 Gebze, Kocaeli, Turkey"},{"name":"Department of Electronics Engineering, University of Turkish Aeronautical Association, 06790 Etimesgut, Ankara, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2023,3,1]]},"reference":[{"key":"S0218126623502237BIB001","first-page":"205","volume-title":"IEEE Radio and Wireless Symp.","author":"Tsai J.-H.","year":"2014"},{"key":"S0218126623502237BIB002","doi-asserted-by":"crossref","first-page":"1151","DOI":"10.1109\/JSSC.2013.2252515","volume":"48","author":"Min S.","year":"2013","journal-title":"IEEE J. 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