{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,25]],"date-time":"2025-12-25T07:20:52Z","timestamp":1766647252911,"version":"3.41.2"},"reference-count":30,"publisher":"World Scientific Pub Co Pte Ltd","issue":"15","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,10]]},"abstract":"<jats:p> In public-key cryptography, the RSA algorithm is an inevitable part of hardware security because of the ease of implementation and security. RSA Cryptographic algorithm uses many modular arithmetic operations that decide the overall performance of the architecture. This paper proposes VLSI architecture to implement an RSA public-key cryptosystem driven by the Residue Number System (RNS). Modular exponentiation in the RSA algorithm is executed by dividing the entire process into modular squaring and multiplication operations. Based on the RNS employment in modulo-exponential operation, two RSA architectures are proposed. A Verilog HDL code is used to model the entire RSA architecture and ported in Zynq FPGA (XC7Z020CLG484-1) for Proof of Concept (PoC). The Cadence Genus Synthesizer tool characterizes a system\u2019s performance for TSMCs standard Cell library. Partial RNS (Proposed-I)- and Fully RNS (Proposed-II)-based RSA architectures increase the operation speed by 13% and 35%, respectively, compared with the existing RSA.\u00a0Even though there is an increase in parameters like area, power and PDP for a smaller key size, the improvement in area utilization and encryption\/ decryption speed of RSA for a larger key size is evident from the analysis. <\/jats:p>","DOI":"10.1142\/s0218126623502559","type":"journal-article","created":{"date-parts":[[2023,3,10]],"date-time":"2023-03-10T07:04:40Z","timestamp":1678431880000},"source":"Crossref","is-referenced-by-count":5,"title":["High-Performance Multi-RNS-Assisted Concurrent RSA Cryptosystem Architectures"],"prefix":"10.1142","volume":"32","author":[{"given":"S.","family":"Elango","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu 638401, India"}]},{"given":"P.","family":"Sampath","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Dr. N.G.P Institute of Technology, Coimbatore, Tamil Nadu 641048, India"}]},{"given":"S.","family":"Raja Sekar","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu 638401, India"}]},{"given":"Sajan P","family":"Philip","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu 638401, India"}]},{"given":"A.","family":"Danielraj","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu 638401, India"}]}],"member":"219","published-online":{"date-parts":[[2023,4,21]]},"reference":[{"key":"S0218126623502559BIB001","volume-title":"Solutions Manual for Cryptography and Network Security: Principles and Practice","author":"Stallings W.","year":"2013","edition":"6"},{"key":"S0218126623502559BIB002","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1109\/MCOM.1978.1089778","volume":"16","author":"Adleman L. M.","year":"1978","journal-title":"IEEE Commun. Soc. Mag."},{"key":"S0218126623502559BIB003","doi-asserted-by":"crossref","first-page":"198","DOI":"10.1109\/TIT.1983.1056650","volume":"29","author":"Dolev D.","year":"1983","journal-title":"IEEE Trans. Inf. Theory"},{"key":"S0218126623502559BIB004","doi-asserted-by":"crossref","first-page":"469","DOI":"10.1109\/TIT.1985.1057074","volume":"31","author":"Elgamal T.","year":"1985","journal-title":"IEEE Trans. Inf. Theory"},{"key":"S0218126623502559BIB005","doi-asserted-by":"crossref","first-page":"500","DOI":"10.1109\/TCE.2015.7389805","volume":"61","author":"Ju H.","year":"2015","journal-title":"IEEE Trans. Consum. Electron."},{"key":"S0218126623502559BIB006","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1109\/MCE.2017.2684940","volume":"6","author":"Sengupta A.","year":"2017","journal-title":"IEEE Consum. Electron. Mag."},{"key":"S0218126623502559BIB007","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1109\/MCAS.2016.2614714","volume":"16","author":"Sousa L.","year":"2016","journal-title":"IEEE Circuits Syst. Mag."},{"key":"S0218126623502559BIB008","doi-asserted-by":"crossref","first-page":"290","DOI":"10.1049\/iet-cdt.2011.0074","volume":"6","author":"Nedjah N.","year":"2012","journal-title":"IET Comput. Digit. Tech."},{"key":"S0218126623502559BIB009","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1109\/MSP.2010.150","volume":"8","author":"Kenny J. R.","year":"2010","journal-title":"IEEE Secur. Priv."},{"key":"S0218126623502559BIB010","doi-asserted-by":"crossref","first-page":"1283","DOI":"10.1109\/JPROC.2014.2335155","volume":"102","author":"Rostami M.","year":"2014","journal-title":"Proc. IEEE"},{"key":"S0218126623502559BIB011","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/MSEC.2019.2923973","volume":"17","author":"Tschofenig H.","year":"2019","journal-title":"IEEE Secur. Priv."},{"key":"S0218126623502559BIB012","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/MC.2016.225","volume":"49","author":"Hu W.","year":"2016","journal-title":"Computer"},{"key":"S0218126623502559BIB013","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/MCAS.2015.2484118","volume":"15","author":"Chang C. H.","year":"2015","journal-title":"IEEE Circuits Syst. Mag."},{"key":"S0218126623502559BIB015","doi-asserted-by":"crossref","first-page":"1545","DOI":"10.1109\/TVLSI.2012.2210916","volume":"21","author":"Esmaeildoust M.","year":"2013","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"S0218126623502559BIB016","doi-asserted-by":"crossref","first-page":"2050214","DOI":"10.1142\/S021812662050214X","volume":"29","author":"Elango S.","year":"2020","journal-title":"J. Circuits, Syst. Comput."},{"key":"S0218126623502559BIB017","first-page":"71","volume":"50","author":"Sekar E.","year":"2020","journal-title":"Inf. MIDEM"},{"key":"S0218126623502559BIB018","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1016\/j.jnca.2014.09.021","volume":"59","author":"Celesti A.","year":"2016","journal-title":"J. Netw. Comput. Appl."},{"key":"S0218126623502559BIB019","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"62","DOI":"10.1007\/978-3-540-28632-5_5","volume-title":"Cryptographic Hardware and Embedded Systems \u2014 CHES 2004","volume":"3156","author":"Bajard J. C.","year":"2004"},{"key":"S0218126623502559BIB020","first-page":"1","volume-title":"Proc. \u2014 2016 11th IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era, DTIS 2016","author":"Fournaris A. P.","year":"2016"},{"key":"S0218126623502559BIB021","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-319-41385-3_8","volume-title":"Residue Number Systems: Theory and Applications","author":"Ananda Mohan P. V.","year":"2016"},{"key":"S0218126623502559BIB022","doi-asserted-by":"crossref","first-page":"903","DOI":"10.1007\/s13369-017-2797-3","volume":"43","author":"Fathy K. A.","year":"2018","journal-title":"Arab. J. Sci. Eng."},{"key":"S0218126623502559BIB024","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126619300034"},{"issue":"8","key":"S0218126623502559BIB025","doi-asserted-by":"crossref","first-page":"4091","DOI":"10.3390\/app12084091","volume":"12","author":"Rashid M.","year":"2022","journal-title":"Appl. Sci."},{"issue":"7","key":"S0218126623502559BIB026","doi-asserted-by":"crossref","first-page":"1131","DOI":"10.3390\/electronics11071131","volume":"11","author":"Umer U.","year":"2022","journal-title":"Electronics"},{"issue":"15","key":"S0218126623502559BIB027","doi-asserted-by":"crossref","first-page":"7079","DOI":"10.3390\/app11157079","volume":"11","author":"Rashid M.","year":"2021","journal-title":"Appl. Sci."},{"key":"S0218126623502559BIB028","doi-asserted-by":"crossref","first-page":"88498","DOI":"10.1109\/ACCESS.2021.3090216","volume":"9","author":"Rashid M.","year":"2021","journal-title":"IEEE Access"},{"key":"S0218126623502559BIB029","doi-asserted-by":"crossref","first-page":"156","DOI":"10.1109\/TE.2010.2048329","volume":"54","author":"Navi K.","year":"2011","journal-title":"IEEE Trans. Edu."},{"key":"S0218126623502559BIB030","first-page":"4","volume-title":"Proc. \u2014 IEEE Int. Symp. Circuits Syst.","author":"Wang W.","year":"2003"},{"key":"S0218126623502559BIB031","first-page":"397","volume-title":"Information Security and Cryptology \u2014 ICISC 2001","author":"Yen S. M.","year":"2002"},{"key":"S0218126623502559BIB032","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2400682.2400692","volume":"9","author":"Antao S.","year":"2013","journal-title":"Trans. Archit. Code Optim."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126623502559","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,10]],"date-time":"2023-10-10T07:48:33Z","timestamp":1696924113000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126623502559"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,21]]},"references-count":30,"journal-issue":{"issue":"15","published-print":{"date-parts":[[2023,10]]}},"alternative-id":["10.1142\/S0218126623502559"],"URL":"https:\/\/doi.org\/10.1142\/s0218126623502559","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2023,4,21]]},"article-number":"2350255"}}