{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T18:22:40Z","timestamp":1769192560093,"version":"3.49.0"},"reference-count":27,"publisher":"World Scientific Pub Co Pte Ltd","issue":"05","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274052"],"award-info":[{"award-number":["62274052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62174001"],"award-info":[{"award-number":["62174001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62027815"],"award-info":[{"award-number":["62027815"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61834006"],"award-info":[{"award-number":["61834006"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Cooperative education project of the Ministry of Education","award":["220803303162437"],"award-info":[{"award-number":["220803303162437"]}]},{"name":"Key Research and Development Projects in Anhui Province","award":["202304a05020003"],"award-info":[{"award-number":["202304a05020003"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2024,3,30]]},"abstract":"<jats:p> The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C<jats:sup>2<\/jats:sup>P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C<jats:sup>2<\/jats:sup>N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C<jats:sup>2<\/jats:sup>P-C<jats:sup>2<\/jats:sup>N, DMR-C<jats:sup>2<\/jats:sup>P and DMR-C<jats:sup>2<\/jats:sup>N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C<jats:sup>2<\/jats:sup>N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. <\/jats:p>","DOI":"10.1142\/s0218126624500920","type":"journal-article","created":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T03:48:00Z","timestamp":1694576880000},"source":"Crossref","is-referenced-by-count":3,"title":["Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy"],"prefix":"10.1142","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8695-4478","authenticated-orcid":false,"given":"Zhengfeng","family":"Huang","sequence":"first","affiliation":[{"name":"School of Microelectronics, Hefei University of Technology, Hefei, Anhui 230601, P. R. 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China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6272-8660","authenticated-orcid":false,"given":"Tianming","family":"Ni","sequence":"additional","affiliation":[{"name":"College of Electrical Engineering, Anhui Polytechnic University, Wuhu, Anhui 241000, P. R. China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7082-4211","authenticated-orcid":false,"given":"Tai","family":"Song","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, Anhui 230601, P. R. China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0024-987X","authenticated-orcid":false,"given":"Aibin","family":"Yan","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Hefei University of Technology, Hefei, Anhui 230601, P. R. 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