{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:06:59Z","timestamp":1753880819040,"version":"3.41.2"},"reference-count":42,"publisher":"World Scientific Pub Co Pte Ltd","issue":"09","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2024,6]]},"abstract":"<jats:p> This paper investigates In[Formula: see text]Ga[Formula: see text]As\/Ga[Formula: see text]As[Formula: see text]Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga[Formula: see text]As[Formula: see text]Sb in the source region and In[Formula: see text]Ga[Formula: see text]As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb\/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb\/Si DMSDG-HJTFET), under the influence of group III\u2013V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO<jats:sub>2<\/jats:sub> as dielectric stack over SiO<jats:sub>2<\/jats:sub> provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga[Formula: see text]As[Formula: see text]Sb\/In[Formula: see text]Ga[Formula: see text]As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool. <\/jats:p>","DOI":"10.1142\/s0218126624501561","type":"journal-article","created":{"date-parts":[[2023,11,28]],"date-time":"2023-11-28T13:55:55Z","timestamp":1701179755000},"source":"Crossref","is-referenced-by-count":2,"title":["Investigation of In0.7Ga0.3As\/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability"],"prefix":"10.1142","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8702-2573","authenticated-orcid":false,"given":"Priyanka","family":"Verma","sequence":"first","affiliation":[{"name":"Jaypee Institute of Information Technology, Department of Electronics and Communication Engineering, Sector-128, Noida 201304, Uttar Pradesh, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8545-2505","authenticated-orcid":false,"given":"Satyendra","family":"Kumar","sequence":"additional","affiliation":[{"name":"Jaypee Institute of Information Technology, Department of Electronics and Communication Engineering, Sector-128, Noida 201304, Uttar Pradesh, India"}]}],"member":"219","published-online":{"date-parts":[[2023,12,22]]},"reference":[{"key":"S0218126624501561BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2006.871855"},{"key":"S0218126624501561BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.901273"},{"key":"S0218126624501561BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/16.19942"},{"key":"S0218126624501561BIB004","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2013.13.3.224"},{"key":"S0218126624501561BIB005","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126620502357"},{"key":"S0218126624501561BIB006","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126618500469"},{"key":"S0218126624501561BIB007","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.49.04DJ12"},{"key":"S0218126624501561BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2052167"},{"key":"S0218126624501561BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070470"},{"key":"S0218126624501561BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2018.2877753"},{"key":"S0218126624501561BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2474147"},{"key":"S0218126624501561BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2295238"},{"key":"S0218126624501561BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2715853"},{"key":"S0218126624501561BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3056632"},{"key":"S0218126624501561BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2365413"},{"key":"S0218126624501561BIB016","doi-asserted-by":"publisher","DOI":"10.1109\/20.800623"},{"key":"S0218126624501561BIB017","doi-asserted-by":"publisher","DOI":"10.1155\/2014\/124814"},{"key":"S0218126624501561BIB018","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2734943"},{"key":"S0218126624501561BIB019","doi-asserted-by":"publisher","DOI":"10.1109\/ICACFCT53978.2021.9837374"},{"key":"S0218126624501561BIB020","first-page":"8","volume-title":"Proc. 5th Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop","author":"Hhuang Z. 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