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Additionally, SMART\u2019s low latency is highly dependent on [Formula: see text], which represents the maximum number of hops traversed within a cycle. Therefore, this paper presents SMART-PG, a power gating method based on SMART that reduces network power consumption by shutting down idle components such as router buffers under low-load conditions. We also extend the router architecture to enable the continuous establishment of single-cycle multi-hop bypass paths. Compared to SMART routers, our method eliminates packet buffering even when a packet reaches the last router of a single-cycle multi-hop path, reducing packet latency and sensitivity to [Formula: see text]. Finally, we propose a routing algorithm that enables efficient packet transmission in one-dimensional and two-dimensional networks even when routers are powered off. Experimental results show that our method reduces packet latency and static power consumption by an average of 7.5% and 46.4%, respectively, compared to the baseline router. Compared to SMART routers, our method demonstrates significant superiority in terms of packet latency and the impact of multi-hop length on packet latency. <\/jats:p>","DOI":"10.1142\/s021812662450172x","type":"journal-article","created":{"date-parts":[[2023,12,12]],"date-time":"2023-12-12T08:25:58Z","timestamp":1702369558000},"source":"Crossref","is-referenced-by-count":2,"title":["Applying SMART-Based Power Gating Approach in NoC System"],"prefix":"10.1142","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1014-8562","authenticated-orcid":false,"given":"Yiming","family":"Ouyang","sequence":"first","affiliation":[{"name":"School of Computer and Information, Hefei University of Technology, 485 Danxia Road, Hefei, Anhui 230601, P. R. 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