{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T00:21:57Z","timestamp":1769214117995,"version":"3.49.0"},"reference-count":32,"publisher":"World Scientific Pub Co Pte Ltd","issue":"10","funder":[{"name":"National Natural Science Foundation of China under grants","award":["61834006"],"award-info":[{"award-number":["61834006"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274502"],"award-info":[{"award-number":["62274502"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274052"],"award-info":[{"award-number":["62274052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62027815"],"award-info":[{"award-number":["62027815"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2024,7,15]]},"abstract":"<jats:p> As the CMOS process continues to decrease in size, the latch becomes increasingly vulnerable to the triple-node-upset (TNU), leading to a decrease in circuit reliability in harsh radiation environments. In this paper, a low-cost TNU self-recovery latch (LCTR) is proposed, which is based on one PMOS and two NMOS (1P2N) inverters and C-elements (CEs) forming a multi-level feedback loop. Due to the error interception function of these fundamental elements, the proposed latch completely realizes TNU self-recovery capability. Then the simulated tests are used for comparing the overhead of the LCTR latch and the other two typical TNU self-recoverable latches. The results reveal that the LCTR latch decreases power consumption by 56.98%, delay by 30.08%, area by 21.25% and PDP by 70.77%, respectively. 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