{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,24]],"date-time":"2025-11-24T07:17:07Z","timestamp":1763968627117,"version":"3.41.2"},"reference-count":27,"publisher":"World Scientific Pub Co Pte Ltd","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2025,3,30]]},"abstract":"<jats:p> In-Memory Computing (IMC) is an emerging paradigm that aims to shift computational workload away from CPUs. The bit-serial IMC architecture suffers from larger latency when performing logic and arithmetic operations. In this paper, a general-purpose, energy-efficient Bit Parallel IMC Architecture (BP-IMCA) based on Area-Optimized (AO-8T) static random access memory (SRAM) bit-cell is proposed to perform In-Memory Boolean Logic Computation (IMBC) and Near-Memory Arithmetic (NMA) operations with variable bit-width from 1- to 8-bit. The decoupled read\/write paths of the employed AO-8T SRAM bit-cell eliminate compute disturbance during IMBC and NMA operations. A self-terminating read word line decoding scheme is proposed to disconnect the RBL discharging path from GND, which decreases the energy consumption of the proposed IMC architecture by 27.71% at 1[Formula: see text]V for IMBC operations. In addition to this, a [Formula: see text]-based Low-offset Symmetric Differential Sense Amplifier (LSDSA) is proposed to achieve fast and reliable sensing for both normal read and IMBC operations in the proposed IMC architecture. Further, a 4[Formula: see text]Kb SRAM array is implemented in 65-nm technology to analyze the IMC architecture at a supply voltage of 1[Formula: see text]V.\u00a0The operating frequency of 1,355[Formula: see text]MHz and average energy consumption of 7.04[Formula: see text]fJ\/bit is achieved during logic (IMBC) operations. The 8-bit addition and 8-bit multiplication operations achieve an energy efficiency of 11.1 TOPS\/W and 2.28 TOPS\/W, respectively, at 1[Formula: see text]V and 970[Formula: see text]MHz. Cumulatively, the proposed architecture achieves the lowest figure of merit compared to the state-of-the-art IMC architectures. <\/jats:p>","DOI":"10.1142\/s0218126625501245","type":"journal-article","created":{"date-parts":[[2024,10,18]],"date-time":"2024-10-18T02:08:59Z","timestamp":1729217339000},"source":"Crossref","is-referenced-by-count":1,"title":["BP-IMCA: An Energy-Efficient 8T SRAM-Based Bit-Parallel In-Memory Computing Architecture"],"prefix":"10.1142","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3876-5514","authenticated-orcid":false,"given":"Anil Kumar","family":"Rajput","sequence":"first","affiliation":[{"name":"VLSI Research Group, ABV-IIITM, Gwalior, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manisha","family":"Pattanaik","sequence":"additional","affiliation":[{"name":"VLSI Research Group, ABV-IIITM, Gwalior, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gaurav","family":"Kaushal","sequence":"additional","affiliation":[{"name":"VLSI Research Group, ABV-IIITM, Gwalior, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2024,12,23]]},"reference":[{"key":"S0218126625501245BIB003","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"S0218126625501245BIB004","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3407588"},{"key":"S0218126625501245BIB005","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-022-02284-0"},{"key":"S0218126625501245BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED51717.2021.9424263"},{"key":"S0218126625501245BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"S0218126625501245BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2023.3297124"},{"key":"S0218126625501245BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2021.3102421"},{"key":"S0218126625501245BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2776309"},{"key":"S0218126625501245BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT50263.2020.9190473"},{"key":"S0218126625501245BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2776302"},{"key":"S0218126625501245BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"S0218126625501245BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"S0218126625501245BIB016","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"S0218126625501245BIB018","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939682"},{"key":"S0218126625501245BIB019","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317741"},{"key":"S0218126625501245BIB020","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218567"},{"key":"S0218126625501245BIB021","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2972528"},{"key":"S0218126625501245BIB022","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105569"},{"key":"S0218126625501245BIB023","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105795"},{"key":"S0218126625501245BIB025","first-page":"110","volume-title":"2023 IEEE 41st Int. Conf. Computer Design (ICCD)","author":"Challagundla D.","year":"2023"},{"key":"S0218126625501245BIB026","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3162602"},{"key":"S0218126625501245BIB027","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2976099"},{"key":"S0218126625501245BIB028","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2915577"},{"key":"S0218126625501245BIB029","first-page":"3503","volume":"68","author":"Chen J.","year":"2021","journal-title":"IEEE Trans. Circuits Syst. II: Express Briefs"},{"key":"S0218126625501245BIB030","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3115970"},{"key":"S0218126625501245BIB032","doi-asserted-by":"publisher","DOI":"10.1109\/INCET49848.2020.9154137"},{"key":"S0218126625501245BIB033","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2004.06.017"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126625501245","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T09:05:31Z","timestamp":1743584731000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126625501245"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,23]]},"references-count":27,"journal-issue":{"issue":"05","published-print":{"date-parts":[[2025,3,30]]}},"alternative-id":["10.1142\/S0218126625501245"],"URL":"https:\/\/doi.org\/10.1142\/s0218126625501245","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2024,12,23]]},"article-number":"2550124"}}