{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:09:27Z","timestamp":1753884567064,"version":"3.41.2"},"reference-count":21,"publisher":"World Scientific Pub Co Pte Ltd","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2025,3,30]]},"abstract":"<jats:p> Power spectral density is a crucial tool in the field of signal processing, mainly in biomedical signal processing. Power spectral density is also one of the most widely used tools in real-time applications. Therefore, further research should be prioritized in the hardware implementation of power spectral density. In this paper, two techniques are introduced in the implementation of power spectral density, mainly focusing on the Fourier transform block. The approaches introduced are the adoption of the Coordinate Rotation Digital Computer algorithm-based fast Fourier transform and the Coordinate Rotation Digital Computer algorithm-based sliding discrete Fourier transform. The other blocks in modified Welch\u2019s architecture are also enhanced using pipelining and approximate distributed arithmetic methods. The introduction of all these techniques has led to an improvement in power and area. There is almost a 36% decrease in the number of lookup tables when compared to the existing methodology. With regards to power, there is almost 44% and 16% decrease in these two architectures, respectively. The overall architectures were synthesized using Xilinx Vivado 19.1, and the language used was Verilog Hardware Description Language. <\/jats:p>","DOI":"10.1142\/s0218126625501270","type":"journal-article","created":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:59:34Z","timestamp":1729652374000},"source":"Crossref","is-referenced-by-count":0,"title":["An Efficient FPGA-Based Welch Power Spectral Density for Real-Time Applications"],"prefix":"10.1142","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4433-2870","authenticated-orcid":false,"given":"Suma","family":"Nair","sequence":"first","affiliation":[{"name":"Department of ECE, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, Tamil Nadu, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5128-4152","authenticated-orcid":false,"given":"Britto Pari","family":"James","sequence":"additional","affiliation":[{"name":"Department of ECE, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, Tamil Nadu, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2024,12,26]]},"reference":[{"key":"S0218126625501270BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/TAU.1967.1161901"},{"key":"S0218126625501270BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342241"},{"key":"S0218126625501270BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/RADAR.2005.1435939"},{"key":"S0218126625501270BIB007","first-page":"39","volume":"21","author":"Kalvikkarasi S.","year":"2017","journal-title":"Int. J. Knowl.-based Intell. Eng. Sys."},{"key":"S0218126625501270BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TPWRS.2022.3229255"},{"key":"S0218126625501270BIB009","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2019.0512"},{"key":"S0218126625501270BIB010","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8121397"},{"key":"S0218126625501270BIB011","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.04.003"},{"key":"S0218126625501270BIB012","volume":"116","author":"Joshi S. M.","year":"2015","journal-title":"Int. J. Comput. Appl."},{"key":"S0218126625501270BIB013","doi-asserted-by":"publisher","DOI":"10.1186\/s13634-022-00855-6"},{"key":"S0218126625501270BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2019.2922751"},{"key":"S0218126625501270BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2022.3182545"},{"key":"S0218126625501270BIB017","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3153050"},{"key":"S0218126625501270BIB018","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2016.0375"},{"key":"S0218126625501270BIB019","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-018-0810-z"},{"key":"S0218126625501270BIB020","volume-title":"Understanding Digital Signal Processing","author":"Lyons R. G.","year":"1997","edition":"3"},{"key":"S0218126625501270BIB023","first-page":"3684","volume":"70","author":"Paz P.","year":"2023","journal-title":"IEEE Trans. Circuits Syst. II: Exp. Briefs"},{"key":"S0218126625501270BIB024","doi-asserted-by":"publisher","DOI":"10.1524\/9783486593501"},{"key":"S0218126625501270BIB025","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-017-11577-3"},{"key":"S0218126625501270BIB027","doi-asserted-by":"publisher","DOI":"10.1161\/01.CIR.101.23.e215"},{"key":"S0218126625501270BIB028","doi-asserted-by":"publisher","DOI":"10.1109\/ICGCCEE.2014.6922467"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126625501270","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T09:02:22Z","timestamp":1743584542000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126625501270"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,26]]},"references-count":21,"journal-issue":{"issue":"05","published-print":{"date-parts":[[2025,3,30]]}},"alternative-id":["10.1142\/S0218126625501270"],"URL":"https:\/\/doi.org\/10.1142\/s0218126625501270","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2024,12,26]]},"article-number":"2550127"}}