{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:19:09Z","timestamp":1753881549099,"version":"3.41.2"},"reference-count":38,"publisher":"World Scientific Pub Co Pte Ltd","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2025,7,15]]},"abstract":"<jats:p> This paper addresses the frequency compensation in a three-stage amplifier for a large capacitive load of 1[Formula: see text]nF. The proposed circuit-1 uses a Self-Cascode (SC) structure in the first stage and an active left-half-plane (LHP) zero circuit at the output of the second stage to cancel the parasitic pole. A Miller capacitor and resistor are also employed in the outer loop to solve the Right Half Plane (RHP) zero issue. A DTMOS transistor along with SC is used in the proposed circuit-2 for enhancing the gain-bandwidth product (GBW). Additionally, a feed forward path is employed to improve the large signal response. The functionality and performance of the proposed amplifiers is examined using TSMC 0.18[Formula: see text][Formula: see text]m CMOS process in Tanner tool. The proposed amplifiers show a maximum GBW, minimum phase margin, and slew rate of 5.2[Formula: see text]MHz, 60<jats:sup>\u2218<\/jats:sup> and 0.1[Formula: see text]V\/[Formula: see text]S, respectively. The maximum Common Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio (PSRR) are observed to be 236[Formula: see text]dB and 84.8[Formula: see text]dB, respectively. To confirm the robustness of the proposed amplifiers, corner analysis has also been done. <\/jats:p>","DOI":"10.1142\/s0218126625502263","type":"journal-article","created":{"date-parts":[[2025,2,15]],"date-time":"2025-02-15T05:11:51Z","timestamp":1739596311000},"source":"Crossref","is-referenced-by-count":0,"title":["Frequency Compensation of Three-Stage Amplifier with Self-Cascode Structure and DTMOS Transistor with Active LHP Zero Circuit"],"prefix":"10.1142","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-6949-5717","authenticated-orcid":false,"given":"Om Krishna","family":"Gupta","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Delhi Technological University, New Delhi 110042, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2911-7061","authenticated-orcid":false,"given":"Neeta","family":"Pandey","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Delhi Technological University, New Delhi 110042, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2495-678X","authenticated-orcid":false,"given":"Maneesha","family":"Gupta","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Netaji Subhas University of Technology, New Delhi 110078, India"}]}],"member":"219","published-online":{"date-parts":[[2025,4,5]]},"reference":[{"key":"S0218126625502263BIB001","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2014.05.007"},{"key":"S0218126625502263BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.900170"},{"key":"S0218126625502263BIB003","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2007.05.003"},{"key":"S0218126625502263BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/82.933799"},{"key":"S0218126625502263BIB005","first-page":"599","volume-title":"IEEE Int. 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