{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:04:29Z","timestamp":1753884269262,"version":"3.41.2"},"reference-count":25,"publisher":"World Scientific Pub Co Pte Ltd","issue":"15","funder":[{"DOI":"10.13039\/501100013058","name":"Jiangsu Provincial Key Research and Development Program","doi-asserted-by":"publisher","award":["BE2023019-3"],"award-info":[{"award-number":["BE2023019-3"]}],"id":[{"id":"10.13039\/501100013058","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2025,10]]},"abstract":"<jats:p> In traditional two-step (TS) counters, the absence of a direct connection between coarse and fine quantization counters necessitates an error calibration block, complicating circuit and timing design. To solve the problem, this paper proposes a TS hold-and-go double-data-rate (TS-HG-DDR) counter for column low-power single-slope analog-to-digital converter (SS ADC) in CMOS image sensors. A TS counting logic with an HG algorithm is proposed, allowing the counter to selectively operate in either ([Formula: see text])-bit fine or M-bit coarse quantization modes without calibration. With the HG algorithm, the counter implements digital correlated double sampling without additional modules such as a bit-wise inversion (BWI) structure, thereby reducing the area. Moreover, a DDR structure that only records the parity information is employed to reduce power consumption. The TS-HG-DDR counter is implemented in a 10-bit column-parallel SS ADC using a 55[Formula: see text]nm CMOS process, with 2.5[Formula: see text]V analog and 1.2[Formula: see text]V digital supplies. As a result, the TS-HG-DDR counter achieves a power consumption reduction of up to 32.6% compared to a TS-BWI counter. The SS ADC has a total power consumption of 27.4[Formula: see text] [Formula: see text]W, with the proposed counter consuming 0.77[Formula: see text] [Formula: see text]W. The differential and integral nonlinearities of the SS ADC are +0.36\/[Formula: see text]0.38 LSB and +0.52\/[Formula: see text]0.95 LSB, respectively. <\/jats:p>","DOI":"10.1142\/s0218126625503268","type":"journal-article","created":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T04:28:40Z","timestamp":1743827320000},"source":"Crossref","is-referenced-by-count":0,"title":["A Low-Power Two-Step Hold-and-Go Counter Without Calibration for Single-Slope ADC in CMOS Image Sensors"],"prefix":"10.1142","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-1630-7602","authenticated-orcid":false,"given":"Taotao","family":"Zhou","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Jiangnan University, Wuxi 214122, P.\u00a0R.\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0624-7461","authenticated-orcid":false,"given":"Xiaoyu","family":"Zhong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Jiangnan University, Wuxi 214122, P.\u00a0R.\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-5061-5411","authenticated-orcid":false,"given":"Sikai","family":"Zhong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Jiangnan University, Wuxi 214122, P.\u00a0R.\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8299-6451","authenticated-orcid":false,"given":"Xiaofeng","family":"Gu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Jiangnan University, Wuxi 214122, P.\u00a0R.\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3435-8628","authenticated-orcid":false,"given":"Zhiguo","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Jiangnan University, Wuxi 214122, P.\u00a0R.\u00a0China"}]}],"member":"219","published-online":{"date-parts":[[2025,6,7]]},"reference":[{"key":"S0218126625503268BIB001","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126624300083"},{"key":"S0218126625503268BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2023.3290103"},{"key":"S0218126625503268BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731675"},{"key":"S0218126625503268BIB004","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492514"},{"key":"S0218126625503268BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2476786"},{"key":"S0218126625503268BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/ICICM56102.2022.10011249"},{"key":"S0218126625503268BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2024.3455317"},{"key":"S0218126625503268BIB008","first-page":"3258","volume":"70","author":"K\u0142osowski M.","year":"2023","journal-title":"IEEE Trans. Circuits Syst. II Exp. Briefs"},{"key":"S0218126625503268BIB009","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105630"},{"key":"S0218126625503268BIB010","first-page":"932","volume":"62","author":"Kim M. K.","year":"2015","journal-title":"IEEE Trans. Circuits Syst. II Exp. Briefs"},{"key":"S0218126625503268BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3059909"},{"key":"S0218126625503268BIB012","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2019.2957043"},{"key":"S0218126625503268BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2587721"},{"key":"S0218126625503268BIB014","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268690"},{"key":"S0218126625503268BIB015","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2018.10.001"},{"key":"S0218126625503268BIB016","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105798"},{"key":"S0218126625503268BIB017","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1109-5"},{"key":"S0218126625503268BIB018","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2020.106865"},{"key":"S0218126625503268BIB020","doi-asserted-by":"publisher","DOI":"10.1049\/el:20072490"},{"key":"S0218126625503268BIB021","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2661843"},{"key":"S0218126625503268BIB022","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2702624"},{"key":"S0218126625503268BIB023","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2959486"},{"key":"S0218126625503268BIB025","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105768"},{"key":"S0218126625503268BIB026","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2023.03.009"},{"key":"S0218126625503268BIB027","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105918"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126625503268","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T03:40:27Z","timestamp":1751341227000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126625503268"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,7]]},"references-count":25,"journal-issue":{"issue":"15","published-print":{"date-parts":[[2025,10]]}},"alternative-id":["10.1142\/S0218126625503268"],"URL":"https:\/\/doi.org\/10.1142\/s0218126625503268","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2025,6,7]]},"article-number":"2550326"}}