{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,18]],"date-time":"2025-10-18T00:11:27Z","timestamp":1760746287171,"version":"build-2065373602"},"reference-count":35,"publisher":"World Scientific Pub Co Pte Ltd","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2026,1,30]]},"abstract":"<jats:p> Regenerative dynamic comparators are becoming more powerful and quicker due to the growing demand for low-voltage, high-speed and power-efficient analog-to-digital converters (ADCs). In this work, two inverter circuits are introduced between the pre-amplifier stage and latch stage of the dynamic comparator. This proposed comparator contributes to a decrease in a metastable state, which results in faster metastability resolution and enhanced small differential input detection. This is achieved using inverters placed after the preamplifier stage. These inverters boost the transconductance, which increases the signal strength applied to the latch stage. The proposed comparator\u2019s delay calculation is done using mathematical analysis. The simulations of the parameters of the proposed comparator are done on the cadence software with 90[Formula: see text]nm and 180[Formula: see text]nm CMOS technology. This design is simulated with a 2[Formula: see text]GHz clock frequency at the supply voltage of 1[Formula: see text]V. This design consumes power of 27.08[Formula: see text]\u00a0[Formula: see text]W and a delay of 89.38 ps at 1[Formula: see text]V supply voltage, 50 mV input difference voltage ([Formula: see text]) and 0.9[Formula: see text]V common mode voltage ([Formula: see text]. This design has a slew rate of nearly 20[Formula: see text]V\/ns. However, [Formula: see text] is at 0.01[Formula: see text]mV with a [Formula: see text] of 0.9[Formula: see text]V which consumes power of 33.83[Formula: see text]\u00a0[Formula: see text]W and a delay of 168.33 ps at 1[Formula: see text]V supply voltage. This paper also illustrates the Monte Carlo simulation of the proposed design\u00a0for power and offset. Analysis of the process corners for power, delay and power delay product (PDP) is carried out. <\/jats:p>","DOI":"10.1142\/s0218126625503657","type":"journal-article","created":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T04:28:01Z","timestamp":1747801681000},"source":"Crossref","is-referenced-by-count":0,"title":["Low-Power, Sensing Small Differential Input Signal of High Speed Dynamic Comparator with Transconductance-Improved Latching Stage"],"prefix":"10.1142","volume":"35","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5486-6358","authenticated-orcid":false,"given":"Anurag","family":"Yadav","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Institute of Engineering and Technology, A.K.T.U., Lucknow, Uttar Pradesh, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2072-5781","authenticated-orcid":false,"given":"Subodh","family":"Wairya","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Institute of Engineering and Technology, A.K.T.U., Lucknow, Uttar Pradesh, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2025,6,30]]},"reference":[{"key":"S0218126625503657BIB001","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2021.153682"},{"key":"S0218126625503657BIB002","doi-asserted-by":"publisher","DOI":"10.1007\/s11277-021-09201-9"},{"key":"S0218126625503657BIB003","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126619500932"},{"key":"S0218126625503657BIB004","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126623501992"},{"key":"S0218126625503657BIB005","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-021-01950-8"},{"key":"S0218126625503657BIB006","doi-asserted-by":"publisher","DOI":"10.1002\/eng2.12055"},{"key":"S0218126625503657BIB007","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126619500221"},{"key":"S0218126625503657BIB008","doi-asserted-by":"publisher","DOI":"10.1142\/S021812662050084X"},{"key":"S0218126625503657BIB009","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2022.154116"},{"key":"S0218126625503657BIB010","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-021-01891-2"},{"key":"S0218126625503657BIB011","doi-asserted-by":"publisher","DOI":"10.1007\/s11277-021-08512-1"},{"key":"S0218126625503657BIB012","first-page":"2675","volume":"68","author":"Aiello O.","year":"2021","journal-title":"IEEE Trans. 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