{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:33:50Z","timestamp":1771698830696,"version":"3.50.1"},"reference-count":17,"publisher":"World Scientific Pub Co Pte Ltd","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2026,1,30]]},"abstract":"<jats:p> Resistive random access memory (RRAM)-based memory technologies have gained attention due to their potential for high-density, low-power, compatibility with CMOS processes, and fast-access memory. They can be integrated into various memory architectures, including tertiary content addressable memory (TCAM). TCAMs are vital to integrated circuits designed for content-based search engines, database systems, and network routers. RRAM-based TCAM has gained significant attention as a promising technology for pattern search and large-scale pattern recognition. This work proposes the design and analyses of 20-transistor\/4-RRAM (20T-4R) and 10-transistors\/2-RRAM (10T-2R) nonvolatile TCAM (NV-TCAM). These designs demonstrate a significant reduction in search delay compared to existing solutions and show improvements in energy efficiency per bit. Specifically, the average energy per search (Esearch) for the 20T-4R TCAM cell is 0.280 fJ\/bit\/search, while the search delay for the 10T-2R TCAM cell is 0.343 fJ\/bit\/search. Although the search energy in the 10T-2R TCAM is lower than in the 20T-4R, the 10T-2R offers an overall advantage in terms of area efficiency. These proposed NV-TCAMs are implemented using 18 nm PDK FinFET technology, providing reduced search delay and lower average Esearch compared to previously discussed architectures. <\/jats:p>","DOI":"10.1142\/s0218126625503906","type":"journal-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T09:05:31Z","timestamp":1751015131000},"source":"Crossref","is-referenced-by-count":1,"title":["Design of Hybrid, High-Speed, Nonvolatile Ternary Content Addressable Memory Using CMOS and RRAM"],"prefix":"10.1142","volume":"35","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-6232-4346","authenticated-orcid":false,"given":"Mohit","family":"Gupta","sequence":"first","affiliation":[{"name":"ECE Department, Indian Institute of Information Technology, Allahabad, Prayagraj 211015, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-3851-697X","authenticated-orcid":false,"given":"Ravi S.","family":"Siddanath","sequence":"additional","affiliation":[{"name":"ECE Department, Indian Institute of Information Technology, Allahabad, Prayagraj 211015, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Layak Singh","family":"Yadav","sequence":"additional","affiliation":[{"name":"ECE Department, Indian Institute of Information Technology, Allahabad, Prayagraj 211015, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mudit","family":"Gupta","sequence":"additional","affiliation":[{"name":"ECE Department, Indian Institute of Information Technology, Allahabad, Prayagraj 211015, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7165-1412","authenticated-orcid":false,"given":"Manish","family":"Goswami","sequence":"additional","affiliation":[{"name":"ECE Department, Indian Institute of Information Technology, Allahabad, Prayagraj 211015, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2683-2230","authenticated-orcid":false,"given":"Kavindra","family":"Kandpal","sequence":"additional","affiliation":[{"name":"ECE Department, Indian Institute of Information Technology, Allahabad, Prayagraj 211015, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2025,7,28]]},"reference":[{"key":"S0218126625503906BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2023.3271308"},{"key":"S0218126625503906BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3140407"},{"key":"S0218126625503906BIB003","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126610006141"},{"key":"S0218126625503906BIB004","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126622500712"},{"key":"S0218126625503906BIB005","first-page":"C104","volume-title":"Symp. on VLSI Technology","author":"Li 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