{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T05:00:44Z","timestamp":1768539644452,"version":"3.49.0"},"reference-count":15,"publisher":"World Scientific Pub Co Pte Ltd","issue":"04","funder":[{"name":"NSTC of Taiwan","award":["NSTC 112-2218-E-110-009-"],"award-info":[{"award-number":["NSTC 112-2218-E-110-009-"]}]},{"name":"NSTC of Taiwan","award":["NSTC 112-2221-E-110-063-MY3"],"award-info":[{"award-number":["NSTC 112-2221-E-110-063-MY3"]}]},{"name":"NSTC of Taiwan","award":["NSTC 112-2923-E-006-003-MY3"],"award-info":[{"award-number":["NSTC 112-2923-E-006-003-MY3"]}]},{"name":"NSTC of Taiwan","award":["NSTC 113-2923-E-110-001-"],"award-info":[{"award-number":["NSTC 113-2923-E-110-001-"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2026,2,28]]},"abstract":"<jats:p>When it comes to power systems, both overall performance and efficiency are key factors in the design of the power device drivers. Using multi-level power gating logic, this study developed an active gate driver (AGD) design that is capable of driving the power transistor at different voltage levels. To lessen the amount of power that the AGD consumes, it is equipped with an effective power gating control logic. Additionally, the Four-stage Stability Control Circuit inside of the AGD makes certain that each and every power MOS device contained within the buffer arrays of the Output Stage is equally utilized. For the implementation of the AGD design, the TSMC 180-nm High-voltage (HV) Bipolar-CMOS-DMOS (BCD) process was utilized. The measurement outcomes with [Formula: see text] equal to 2[Formula: see text]nF and an operating PWM frequency of 400[Formula: see text]kHz validate the functionality of the AGD design. It dissipates an average of 533[Formula: see text]mW, which is a combination of static and dynamic power. Finally, the power gating mechanism offers a power reduction of 49.23%, as determined by a comparison of two cycles with and without power gating circuit installed.<\/jats:p>","DOI":"10.1142\/s0218126625504237","type":"journal-article","created":{"date-parts":[[2025,7,28]],"date-time":"2025-07-28T00:10:36Z","timestamp":1753661436000},"source":"Crossref","is-referenced-by-count":1,"title":["A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control"],"prefix":"10.1142","volume":"35","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2426-2879","authenticated-orcid":false,"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[{"name":"Institute of Integrated Circuit Design, National Sun Yat-sen University, No. 70, Lien-hai Road, Gushan, Kaohsiung 80424, Taiwan"},{"name":"Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung City 80424, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-0768-188X","authenticated-orcid":false,"given":"Pradyumna","family":"Vellanki","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-sen University, No. 70, Lien-hai Road, Gushan, Kaohsiung 80424, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soumika","family":"Majumder","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-sen University, No. 70, Lien-hai Road, Gushan, Kaohsiung 80424, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-7310-8323","authenticated-orcid":false,"given":"L S S","family":"Pavan Kumar Chodisettii","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-sen University, No. 70, Lien-hai Road, Gushan, Kaohsiung 80424, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Venkata Naveen","family":"Kolakaluri","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Sun Yat-sen University, No. 70, Lien-hai Road, Gushan, Kaohsiung 80424, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mitch Ming-Chi","family":"Chou","sequence":"additional","affiliation":[{"name":"Academy of Innovative Semiconductor and Sustainable Manufacturing, National Cheng Kung University, Tainan 70101, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8014-8229","authenticated-orcid":false,"given":"Lean Karlo Santos","family":"Tolentino","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, Technological University of the Philippines, Ermita, Manila 1000, Philippines"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2025,8,20]]},"reference":[{"key":"S0218126625504237BIB001","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2013.2271111"},{"key":"S0218126625504237BIB002","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2021.105295"},{"key":"S0218126625504237BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2018.2848900"},{"key":"S0218126625504237BIB004","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2018.2878779"},{"key":"S0218126625504237BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2019.2922824"},{"key":"S0218126625504237BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/ISPSD49238.2022.9813625"},{"key":"S0218126625504237BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/ECCE-Asia49820.2021.9478986"},{"key":"S0218126625504237BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/ISPSD.2019.8757646"},{"key":"S0218126625504237BIB009","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS57524.2023.10406126"},{"key":"S0218126625504237BIB010","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS62602.2024.10808912"},{"key":"S0218126625504237BIB011","doi-asserted-by":"publisher","DOI":"10.1109\/82.754867"},{"key":"S0218126625504237BIB012","first-page":"3083","volume":"68","author":"Yuan B.","year":"2021","journal-title":"IEEE Trans. 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