{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,19]],"date-time":"2025-12-19T01:49:41Z","timestamp":1766108981599,"version":"3.48.0"},"reference-count":44,"publisher":"World Scientific Pub Co Pte Ltd","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2026,3,15]]},"abstract":"<jats:p>\n                    This paper presents two memristor-aided design schemes for the Dynamic Positive Feedback Source Coupled Logic (D-PFSCL) style. A Memristor-based Network (MBN) in combination with a D-PFSCL inverter is used in one scheme and is referred to as MAD1 scheme. The other scheme employs D-PFSCL NOR\/OR gate with MBN and is termed as MAD2 scheme. Mathematical formulations to determine the voltage swing and delay for MAD1-based 2:1 MUX are put forward. The functional verification of the proposed scheme-based 2:1 multiplexer (MUX) is carried out using CMOS PTM 90[Formula: see text]nm technology node parameters and TiO\n                    <jats:sub>2<\/jats:sub>\n                    memristor model. Further, a 4:1 MUX is realized using existing and proposed D-PFSCL schemes to illustrate the advantage of the proposed schemes. It is found that the maximum improvement in area for MAD1 2:1 MUX and 4:1 MUX is 32% and 75%, respectively, with respect to the recently presented transmission gate-based D-PFSCL MUX. The delay [Formula: see text], power and Power Delay Product (PDP) results follow the same trend. Lastly, the effect of technology scaling, process variation on the performance is also examined.\n                  <\/jats:p>","DOI":"10.1142\/s0218126625504390","type":"journal-article","created":{"date-parts":[[2025,8,7]],"date-time":"2025-08-07T10:03:01Z","timestamp":1754560981000},"source":"Crossref","is-referenced-by-count":0,"title":["Memristor-Aided Dynamic Positive Feedback Source Coupled Logic"],"prefix":"10.1142","volume":"35","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-4443-2318","authenticated-orcid":false,"given":"Shikha","family":"Mouria","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India"},{"name":"Bharati Vidyapeeth\u2019s College of Engineering, Delhi 110063, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2911-7061","authenticated-orcid":false,"given":"Neeta","family":"Pandey","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0565-0654","authenticated-orcid":false,"given":"Kirti","family":"Gupta","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Bharati Vidyapeeth\u2019s College of Engineering, Delhi 110063, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2025,9,6]]},"reference":[{"key":"S0218126625504390BIB001","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-15-0982-7"},{"key":"S0218126625504390BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/iNIS.2017.45"},{"volume-title":"Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits","year":"2006","author":"Alioto M.","key":"S0218126625504390BIB003"},{"key":"S0218126625504390BIB004","doi-asserted-by":"publisher","DOI":"10.1002\/cta.305"},{"key":"S0218126625504390BIB005","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.838149"},{"key":"S0218126625504390BIB006","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.904685"},{"key":"S0218126625504390BIB007","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCT.2011.6075165"},{"key":"S0218126625504390BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/INDICON.2015.7443260"},{"key":"S0218126625504390BIB009","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.05.002"},{"key":"S0218126625504390BIB010","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2016.1138519"},{"key":"S0218126625504390BIB011","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2020.05.004"},{"key":"S0218126625504390BIB012","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2022.104521"},{"key":"S0218126625504390BIB013","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"S0218126625504390BIB014","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-4491-2"},{"key":"S0218126625504390BIB015","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2014.2334701"},{"key":"S0218126625504390BIB016","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2019.2899262"},{"key":"S0218126625504390BIB017","first-page":"1009","volume":"37","author":"Xia L.","year":"2017","journal-title":"IEEE Trans. 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