{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T09:06:53Z","timestamp":1761988013720},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[1991,6]]},"abstract":"<jats:p> All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employing these multipliers, large-scale artificial neural networks can be implemented using fewer MOS transistors than are required by implementations employing the so-called Gilbert multiplier. <\/jats:p><jats:p> PSPICE circuit simulations have been extensively executed in order to quantify the performance of these multipliers by measuring the following specifications: maximum percentage error, output offset, X or Y nonlinearity, X or Y feedthrough, small-signal bandwidth, and slew rate. <\/jats:p><jats:p> An 11-dimensional analog vector multiplier has been designed on a 40-pin MOSIS TINYCHIP with analog pads using the MAGIC VLSI tools and has been fabricated using 2 \u03bcm CMOS n-well process via MOSIS. <\/jats:p>","DOI":"10.1142\/s0218126691000057","type":"journal-article","created":{"date-parts":[[2004,11,25]],"date-time":"2004-11-25T12:12:21Z","timestamp":1101384741000},"page":"205-228","source":"Crossref","is-referenced-by-count":8,"title":["ANALOG MOS VECTOR MULTIPLIERS FOR THE IMPLEMENTATION OF SYNAPSES IN ARTIFICIAL NEURAL NETWORKS"],"prefix":"10.1142","volume":"01","author":[{"given":"FATHI M.A.","family":"SALAM","sequence":"first","affiliation":[{"name":"Systems and Circuits and Artificial Neural Nets Laboratories, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824, USA"}]},{"given":"MYUNG-RYUL","family":"CHOI","sequence":"additional","affiliation":[{"name":"Systems and Circuits and Artificial Neural Nets Laboratories, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824, USA"}]}],"member":"219","published-online":{"date-parts":[[2012,1,25]]},"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126691000057","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T23:22:40Z","timestamp":1565133760000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126691000057"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,6]]},"references-count":0,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2012,1,25]]},"published-print":{"date-parts":[[1991,6]]}},"alternative-id":["10.1142\/S0218126691000057"],"URL":"https:\/\/doi.org\/10.1142\/s0218126691000057","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[1991,6]]}}}