{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T18:19:39Z","timestamp":1649009979724},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[1991,9]]},"abstract":"<jats:p> In this paper, we describe a special purpose hardware called ESEU (Expandable Shading Engine Unit) for fast rendering of 3-D scenes using Gouraud shading model. Each ESEU has three major functional blocks: linear interpolator, multipliers and Edge Painting Tree. Linear interpolator with coupled binary tree structure yields the functional values at all pixels within each zone (zone denotes the smallest interval which encompasses the given span and consists of 2<jats:sup>n<\/jats:sup> successive pixels in the x-direction, where n is some integer) by interpolating the functional values, such as z-depth values or color intensities, at the left and right end points of the zone which are calculated by the multipliers. Mask pattern for the removal of data for the pixels outside the original span but within the corresponding zone is generated by the Edge Painting Tree. Since there are no interconnections among ESEU\u2019s, graphics system with any screen size can be easily built using a multitude of the prototype ESEU\u2019s. A prototype ESEU in this work handles 64 pixels; therefore, 16 ESEU\u2019s are required for screens having a 1024-pixel width. The bit-serial nature of the prototype ESEU is suitable for its VLSI implementation at a reasonable cost. <\/jats:p>","DOI":"10.1142\/s0218126691000070","type":"journal-article","created":{"date-parts":[[2004,11,25]],"date-time":"2004-11-25T07:12:21Z","timestamp":1101366741000},"page":"239-255","source":"Crossref","is-referenced-by-count":0,"title":["A GRAPHICS ACCELERATOR FOR HIDDEN SURFACE REMOVAL AND COLOR SHADING"],"prefix":"10.1142","volume":"01","author":[{"given":"SEONG-OK","family":"BAE","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, P.O. Box 150, Cheongryang, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"KYUNG-IL","family":"BANG","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, P.O. Box 150, Cheongryang, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"CHONG-MIN","family":"KYUNG","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, P.O. Box 150, Cheongryang, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2012,1,25]]},"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126691000070","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T19:21:44Z","timestamp":1565119304000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126691000070"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,9]]},"references-count":0,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2012,1,25]]},"published-print":{"date-parts":[[1991,9]]}},"alternative-id":["10.1142\/S0218126691000070"],"URL":"https:\/\/doi.org\/10.1142\/s0218126691000070","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[1991,9]]}}}