{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T01:11:11Z","timestamp":1648948271664},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[1996,6]]},"abstract":"<jats:p> A methodology for transforming a class of iterative algorithms, expressed in nested loops, into Uniform Recurrent Equation (URE) forms and their mapping into regular processor array architectures is presented. The propagation space of the variables of the original nested loop is specified by a system of linear equations formed by their index functions. The data flow within the index space, is then localized by the derivation of a set of parametric dependence vectors, which eventually can be used to transform the initial algorithm into a set of UREs. The mapping of the UREs is accomplished by decomposition of the index space into independent subsets of variable instances using the derived dependence vectors. The dependence graphs of the subsets are normalized and subsequently, are mapped on the processor array architecture. The exploitation of the independent subsets leads to significant improvement of the efficiency of the processor array compared to architectures derived by using linear transformations of the entire index space. Under certain conditions, only local interconnections in the processor array are required. The proposed methodology is illustrated by the design of alternative processor arrays implementing the convolution algorithm. <\/jats:p>","DOI":"10.1142\/s0218126696000194","type":"journal-article","created":{"date-parts":[[2004,10,25]],"date-time":"2004-10-25T12:13:15Z","timestamp":1098706395000},"page":"243-265","source":"Crossref","is-referenced-by-count":0,"title":["TRANSFORMATION OF NESTED LOOPS INTO UNIFORM RECURRENCES AND THEIR MAPPING TO REGULAR PROCESSOR ARRAYS"],"prefix":"10.1142","volume":"06","author":[{"given":"E.D.","family":"KYRIAKIS-BITZAROS","sequence":"first","affiliation":[{"name":"Institute of Microelectronics, NCSR \u201cDemokritos\u201d 15310 Agia Paraskevi, Greece"}]},{"given":"D.J.","family":"SOUDRIS","sequence":"additional","affiliation":[{"name":"Laboratory of Electrical and Electronic Material Technology, Department of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, 67100, Greece"}]},{"given":"C.E.","family":"GOUTIS","sequence":"additional","affiliation":[{"name":"VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26100, Greece"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126696000194","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:45:35Z","timestamp":1565149535000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126696000194"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,6]]},"references-count":0,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1996,6]]}},"alternative-id":["10.1142\/S0218126696000194"],"URL":"https:\/\/doi.org\/10.1142\/s0218126696000194","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[1996,6]]}}}