{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T16:55:39Z","timestamp":1648918539597},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[1996,6]]},"abstract":"<jats:p> A unified algorithm is presented to solve the problem of estimation and scheduling for performance constrained data flow graphs. The algorithm achieves superior results by first computing a lower bound on the number of functional units required to satisfy the performance constraint T, and then scheduling the operations into the best control steps using the lower bound algorithm. The lower bound not only greatly reduces the size of the solution space, but also provides a means to measure the proximity of the final solution to an optimal one. Our algorithm is the first one to use a sharp lower bound estimation technique to direct scheduling. In addition, our unified algorithm can easily be incorporated into a branch-and-bound algorithm to solve the scheduling problem optimally. Since our algorithm computes a sharp lower bound, the computation time of an optimal algorithm can be greatly reduced. Experiments indicate that our scheduling algorithm can produce results very close to the lower bound. For all of the test cases the difference between our upper and lower bounds is not greater than one. <\/jats:p>","DOI":"10.1142\/s0218126696000212","type":"journal-article","created":{"date-parts":[[2004,10,25]],"date-time":"2004-10-25T12:13:15Z","timestamp":1098706395000},"page":"287-318","source":"Crossref","is-referenced-by-count":1,"title":["A UNIFIED ALGORITHM FOR THE ESTIMATION AND SCHEDULING OF DATA FLOW GRAPHS"],"prefix":"10.1142","volume":"06","author":[{"given":"YUAN","family":"HU","sequence":"first","affiliation":[{"name":"HaL Computer Systems, 1315 Dell Avenue, Campbell, CA 95008, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"BRADLEY S.","family":"CARLSON","sequence":"additional","affiliation":[{"name":"The NSF Center for the Design of Analog\/Digital Integrated Circuits (CDADIC) and the Department of Electrical Engineering State University of New York at Stony Brook Stony Brook, NY 11794\u20132350, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126696000212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:45:37Z","timestamp":1565149537000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126696000212"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,6]]},"references-count":0,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1996,6]]}},"alternative-id":["10.1142\/S0218126696000212"],"URL":"https:\/\/doi.org\/10.1142\/s0218126696000212","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[1996,6]]}}}