{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T11:50:04Z","timestamp":1648986604527},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[1998,2]]},"abstract":"<jats:p> Petri nets<jats:sup>46,37,45,48<\/jats:sup> are a powerful formalism for modeling concurrent systems. They are capable of implicitly describing a vast state space by a succinct representation which gracefully captures the notions of causality, concurrency and conflict between events. Petri nets have also been chosen by many authors as a formalism to describe the behavior of asynchronous circuits by interpreting the events as signal transitions, thus coining the term Signal Transition Graph (STG).<jats:sup>50,4<\/jats:sup> <\/jats:p><jats:p> A design framework for asynchronous systems involves three main aspects: formal specification, verification and synthesis. In this paper we review the main techniques we have used to cover these aspects in recent years, with a special focus on asynchronous circuits. <\/jats:p>","DOI":"10.1142\/s0218126698000055","type":"journal-article","created":{"date-parts":[[2003,5,27]],"date-time":"2003-05-27T09:25:48Z","timestamp":1054027548000},"page":"67-118","source":"Crossref","is-referenced-by-count":4,"title":["THE USE OF PETRI NETS FOR THE DESIGN AND VERIFICATION OF ASYNCHRONOUS CIRCUITS AND SYSTEMS"],"prefix":"10.1142","volume":"08","author":[{"given":"ALEX","family":"KONDRATYEV","sequence":"first","affiliation":[{"name":"The University of Aizu, Aizu-Wakamatsu, 965-80, Japan"}]},{"given":"MICHAEL","family":"KISHINEVSKY","sequence":"additional","affiliation":[{"name":"The University of Aizu, Aizu-Wakamatsu, 965-80, Japan"}]},{"given":"ALEXANDER","family":"TAUBIN","sequence":"additional","affiliation":[{"name":"The University of Aizu, Aizu-Wakamatsu, 965-80, Japan"}]},{"given":"JORDI","family":"CORTADELLA","sequence":"additional","affiliation":[{"name":"Univ. Politecnica de Catalunya, Barcelona, Spain"}]},{"given":"LUCIANO","family":"LAVAGNO","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, 10129 Torino, Italy"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126698000055","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:47:06Z","timestamp":1565149626000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126698000055"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,2]]},"references-count":0,"journal-issue":{"issue":"01","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1998,2]]}},"alternative-id":["10.1142\/S0218126698000055"],"URL":"https:\/\/doi.org\/10.1142\/s0218126698000055","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[1998,2]]}}}