{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,14]],"date-time":"2024-09-14T14:25:12Z","timestamp":1726323912552},"reference-count":13,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int. J. Soft. Eng. Knowl. Eng."],"published-print":{"date-parts":[[2012,8]]},"abstract":"<jats:p> In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning single and double-fault diagnoses clearly indicates that incorporating test suites into the fault localization technique (and development process) considerably improves the accuracy of the obtained diagnosis candidates. <\/jats:p>","DOI":"10.1142\/s0218194012500209","type":"journal-article","created":{"date-parts":[[2012,10,18]],"date-time":"2012-10-18T12:00:12Z","timestamp":1350561612000},"page":"695-723","source":"Crossref","is-referenced-by-count":4,"title":["AUTOMATED DEBUGGING OF VERILOG DESIGNS"],"prefix":"10.1142","volume":"22","author":[{"given":"BERNHARD","family":"PEISCHL","sequence":"first","affiliation":[{"name":"Softnet Austria, Inffelgasse 16b\/II, 8010 Graz, Austria"}]},{"given":"NAVEED","family":"RIAZ","sequence":"additional","affiliation":[{"name":"Shaheed Zulfikar Ali Bhutto Institute of Science and Technology, 44000 Islamabad, Pakistan"}]},{"given":"FRANZ","family":"WOTAWA","sequence":"additional","affiliation":[{"name":"Institute for Software Technology, Technische Universit\u00e4t Graz, 8010 Graz, Austria"}]}],"member":"219","published-online":{"date-parts":[[2012,10,17]]},"reference":[{"key":"rf1","volume-title":"VHDL Analysis and Modeling of Digital Systems","author":"Navabi Z.","year":"1993"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/45.1.27"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1016\/0004-3702(87)90062-2"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1023\/A:1012821511498"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1016\/S0004-3702(99)00034-X"},{"key":"rf17","doi-asserted-by":"publisher","DOI":"10.1023\/B:APIN.0000033635.98612.1e"},{"key":"rf24","doi-asserted-by":"publisher","DOI":"10.1109\/43.913758"},{"key":"rf26","volume-title":"Model Checking","author":"Clarke M. Edmund","year":"1999"},{"key":"rf27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-04558-9"},{"key":"rf32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1984.1270076"},{"key":"rf34","doi-asserted-by":"publisher","DOI":"10.1109\/43.3141"},{"key":"rf35","first-page":"1385","volume":"12","author":"Pomeranz I.","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"rf37","doi-asserted-by":"publisher","DOI":"10.1016\/j.jss.2009.06.035"}],"container-title":["International Journal of Software Engineering and Knowledge Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218194012500209","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T14:16:29Z","timestamp":1565100989000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218194012500209"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":13,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2012,10,17]]},"published-print":{"date-parts":[[2012,8]]}},"alternative-id":["10.1142\/S0218194012500209"],"URL":"https:\/\/doi.org\/10.1142\/s0218194012500209","relation":{},"ISSN":["0218-1940","1793-6403"],"issn-type":[{"value":"0218-1940","type":"print"},{"value":"1793-6403","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,8]]}}}