{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T07:25:33Z","timestamp":1649057133828},"reference-count":15,"publisher":"World Scientific Pub Co Pte Lt","issue":"03n04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Inter. Net."],"published-print":{"date-parts":[[2010,9]]},"abstract":"<jats:p> Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I\/O permutations of Clos networks, sequential routing algorithms are too slow, and all known parallel algorithms are not practical. We present the algorithm-hardware codesign of a unified fast parallel routing architecture called distributed pipeline routing (DPR) architecture for rearrangeable nonblocking and strictly nonblocking Clos networks. The DPR architecture uses a linear interconnection structure and processing elements that performs only shift and logic AND operations. We show that a DPR architecture can route any permutation in rearrangeable nonblocking and strictly nonblocking Clos networks in [Formula: see text] time. The same architecture can be used to carry out control of any group of connection\/disconnection requests for strictly nonblocking Clos networks in [Formula: see text] time. Several speeding-up techniques are also presented. This architecture is designed for Clos-based packet and circuit switches of practical sizes. <\/jats:p>","DOI":"10.1142\/s0219265910002805","type":"journal-article","created":{"date-parts":[[2011,4,13]],"date-time":"2011-04-13T01:49:04Z","timestamp":1302659344000},"page":"189-210","source":"Crossref","is-referenced-by-count":1,"title":["ALGORITHM-HARDWARE CODESIGN OF A FAST PARALLEL ROUTING ARCHITECTURE FOR CLOS NETWORKS"],"prefix":"10.1142","volume":"11","author":[{"given":"S. Q.","family":"ZHENG","sequence":"first","affiliation":[{"name":"Department of Computer Science, University of Texas at Dallas, Richardson, Texas 75080, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"GUMASTE","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Indian Institute of Technology, Bombay, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"LU","sequence":"additional","affiliation":[{"name":"Department of Mathematics and Computer Science, Salisbury University, Salisbury, Maryland 21801, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1145\/161541.161736"},{"key":"rf2","volume-title":"Mathematical Theory of Connecting Networks and Telephone Traffic","author":"Benes V. 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