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We suggest a neural network-based technique to address this issue, and we put it into practice using FPGAs to handle human speech noise in real time. We refined a neural network architecture for human speech inputs and developed it for FPGA hardware acceleration. The experimental findings demonstrate the tremendous advancements our method makes in real-time and denoising effect, while also showing the potential of PCNN features to improve recognition stability and offer a fresh perspective on how to effectively apply speech processing in embedded systems. The overall improvement of the system was an average of [Formula: see text] [Formula: see text]dB in SNR, and when evaluated in noisy conditions, an additional [Formula: see text] PESQ and [Formula: see text] STOI could be gained. This implementation (on a Xilinx Zynq-7020 FPGA) consumed approximately 21% for LUTs, 18% for DSPs, and 25% for BRAM. It had a latency of 1.8[Formula: see text]ms and 1.2[Formula: see text]W power consumption. The FPGA design turned out to be [Formula: see text] faster than the CPU in standard configurations, which saves over 70% of energy, making it possible to implement real-time speech denoising.<\/jats:p>","DOI":"10.1142\/s1469026825500129","type":"journal-article","created":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T06:46:52Z","timestamp":1762843612000},"source":"Crossref","is-referenced-by-count":0,"title":["FPGA-Deployable PCNN-Based Neural Network Implementation for Real-Time Speech Recognition"],"prefix":"10.1142","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-5668-3021","authenticated-orcid":false,"given":"Hui-Sheng","family":"Zhu","sequence":"first","affiliation":[{"name":"National Cultural Industry Research, Central China Normal University, Wuhan, Hubei 430079, P. R. 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