{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:38Z","timestamp":1750308218164,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,8,9]],"date-time":"2004-08-09T00:00:00Z","timestamp":1092009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,8,9]]},"DOI":"10.1145\/1013235.1013271","type":"proceedings-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T17:39:48Z","timestamp":1097170788000},"page":"120-125","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Location cache"],"prefix":"10.1145","author":[{"given":"Rui","family":"Min","sequence":"first","affiliation":[{"name":"University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen-Ben","family":"Jone","sequence":"additional","affiliation":[{"name":"University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiming","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,8,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224093"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313860"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224090"},{"key":"e_1_3_2_1_4_1","first-page":"248","volume-title":"on-demand cache resource allocation,\" in Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture","author":"Albonesi D. H.","year":"1999","unstructured":"D. H. Albonesi , \"Selective cache ways : on-demand cache resource allocation,\" in Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture , pp. 248 -- 259 , 1999 . D. H. Albonesi, \"Selective cache ways: on-demand cache resource allocation,\" in Proceedings of the 32nd Annual ACM\/IEEE International Symposium on Microarchitecture, pp. 248--259, 1999."},{"key":"e_1_3_2_1_5_1","first-page":"184","volume-title":"The filter cache: an energy efficient memory structure,\" in 30th Annual International Symposium on Microarchitecture (Micro '97)","author":"Kin J.","year":"1997","unstructured":"J. Kin , M. Gupta , and W. Mangione-Smith , \" The filter cache: an energy efficient memory structure,\" in 30th Annual International Symposium on Microarchitecture (Micro '97) , pp. 184 -- 193 , December 1997 . J. Kin, M. Gupta, and W. Mangione-Smith, \"The filter cache: an energy efficient memory structure,\" in 30th Annual International Symposium on Microarchitecture (Micro '97), pp. 184--193, December 1997."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.476254"},{"key":"e_1_3_2_1_7_1","first-page":"356","volume-title":"Data cache design considerations for the itanium2 processor,\" in Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)","author":"Lyon T.","year":"2002","unstructured":"T. Lyon , E. Delano , C. McNairy , and D. Mulla , \" Data cache design considerations for the itanium2 processor,\" in Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02) , pp. 356 -- 362 , 2002 . T. Lyon, E. Delano, C. McNairy, and D. Mulla, \"Data cache design considerations for the itanium2 processor,\" in Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), pp. 356--362, 2002."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"e_1_3_2_1_9_1","first-page":"307","volume-title":"Just say no: Benefits of early cache miss determination,\" in Prod. of the Ninth International Symposium on High-Performance Computer Architecture","author":"Memik G.","year":"2003","unstructured":"G. Memik , G. Reinman , and W. Mangio-Smith , \" Just say no: Benefits of early cache miss determination,\" in Prod. of the Ninth International Symposium on High-Performance Computer Architecture , pp. 307 -- 316 , 2003 . G. Memik, G. Reinman, and W. Mangio-Smith, \"Just say no: Benefits of early cache miss determination,\" in Prod. of the Ninth International Symposium on High-Performance Computer Architecture, pp. 307--316, 2003."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/48012.48037"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/30350.30374"},{"key":"e_1_3_2_1_13_1","first-page":"244","volume-title":"Predictive sequential associative cache,\" in Proc. of the 2nd IEEE Symposium on High-Performance Computer Architecture (HPCA '96)","author":"Calder B.","year":"1996","unstructured":"B. Calder , D. Grunwald , and J. Emer , \" Predictive sequential associative cache,\" in Proc. of the 2nd IEEE Symposium on High-Performance Computer Architecture (HPCA '96) , pp. 244 -- 254 , 1996 . B. Calder, D. Grunwald, and J. Emer, \"Predictive sequential associative cache,\" in Proc. of the 2nd IEEE Symposium on High-Performance Computer Architecture (HPCA '96), pp. 244--254, 1996."},{"key":"e_1_3_2_1_14_1","first-page":"49","volume-title":"International Conference on Parallel Architectures and Compiler Techinques (PACT'01)","author":"Vijaykumar T. N.","year":"2001","unstructured":"T. N. Vijaykumar , \"Reactive-associative caches,\" in International Conference on Parallel Architectures and Compiler Techinques (PACT'01) , pp. 49 -- 61 , 2001 . T. N. Vijaykumar, \"Reactive-associative caches,\" in International Conference on Parallel Architectures and Compiler Techinques (PACT'01), pp. 49--61, 2001."},{"key":"e_1_3_2_1_15_1","first-page":"190","volume-title":"Integrating adaptive on-chip storage structures for reduced dynamic power,\" in International Conference on Parallel Architectures and Compilation Techniques (PACT02)","author":"Buyuktonsunoglu A.","year":"2002","unstructured":"S.Dropsho, A. Buyuktonsunoglu , D. H. A. R. Balasubramonian , G. S. S. Dwarkadas , G. Magklis , and M. Scott , \" Integrating adaptive on-chip storage structures for reduced dynamic power,\" in International Conference on Parallel Architectures and Compilation Techniques (PACT02) , pp. 190 -- 202 , 2002 . S.Dropsho, A. Buyuktonsunoglu, D. H. A. R. Balasubramonian, G. S. S. Dwarkadas, G. Magklis, and M. Scott, \"Integrating adaptive on-chip storage structures for reduced dynamic power,\" in International Conference on Parallel Architectures and Compilation Techniques (PACT02), pp. 190--202, 2002."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313948"},{"key":"e_1_3_2_1_17_1","first-page":"54","volume-title":"Reducing set-associative cache energy via way-prediction and selective direct-mapping,\" in 34th Annual International Symposium on Microarchitecture (MICRO'01)","author":"Powell M.","year":"2001","unstructured":"M. Powell , A. Agrawal , T. Vijaykumar , B. Falsafi , and K. Roy , \" Reducing set-associative cache energy via way-prediction and selective direct-mapping,\" in 34th Annual International Symposium on Microarchitecture (MICRO'01) , pp. 54 -- 65 , December 2001 . M. Powell, A. Agrawal, T. Vijaykumar, B. Falsafi, and K. Roy, \"Reducing set-associative cache energy via way-prediction and selective direct-mapping,\" in 34th Annual International Symposium on Microarchitecture (MICRO'01), pp. 54--65, December 2001."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232986"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192742"},{"key":"e_1_3_2_1_20_1","first-page":"140","volume-title":"of the 8th Great Lakes Symposium on VLSI","author":"Chander K. A., N.","year":"1998","unstructured":"K. A., N. Chander , P. S. , and J. L., \"Modeling and analysis of the difference-bit cache,\" in Proc. of the 8th Great Lakes Symposium on VLSI , pp. 140 -- 145 , 1998 . K. A., N. Chander, P. S., and J. L., \"Modeling and analysis of the difference-bit cache,\" in Proc. of the 8th Great Lakes Symposium on VLSI, pp. 140--145, 1998."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/507052.507055"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566444"},{"key":"e_1_3_2_1_23_1","first-page":"148","volume-title":"Drowsy caches: Simple techniques for reducing leakage power,\" in International Symposium on Computer Architecture","author":"Flautner K.","year":"2002","unstructured":"K. Flautner , N. Kim , S. Martin , D. Blaauw , and T. Mudge , \" Drowsy caches: Simple techniques for reducing leakage power,\" in International Symposium on Computer Architecture , pp. 148 -- 158 , June 2002 . K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge, \"Drowsy caches: Simple techniques for reducing leakage power,\" in International Symposium on Computer Architecture, pp. 148--158, June 2002."},{"key":"e_1_3_2_1_24_1","first-page":"61","volume-title":"Spain)","author":"Zhou H.","year":"2001","unstructured":"H. Zhou , M. C. Toburen , E. Rotenberg , and T. M. Conte , \" Adaptive mode control: A static-power-efficient cache design,\" in International Conference on Parallel Architectures and Compilation Techniques (PACT'01), (Barcelona , Spain) , pp. 61 -- 73 , September 2001 . H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte, \"Adaptive mode control: A static-power-efficient cache design,\" in International Conference on Parallel Architectures and Compilation Techniques (PACT'01), (Barcelona, Spain), pp. 61--73, September 2001."},{"key":"e_1_3_2_1_25_1","first-page":"922","volume-title":"Cache energy reduction by dual voltage supply,\" in The 2001 IEEE International Symposium on Circuits and Systems (ISCAS","author":"Moshnyaga V.","year":"2001","unstructured":"V. Moshnyaga and H. Tsuji , \" Cache energy reduction by dual voltage supply,\" in The 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001 ), pp. 922 -- 925 , May 2001. V. Moshnyaga and H. Tsuji, \"Cache energy reduction by dual voltage supply,\" in The 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001), pp. 922--925, May 2001."},{"key":"e_1_3_2_1_26_1","first-page":"197","volume-title":"Energy efficient frequent value data cache design,\" in IEEE\/ACM 35th International Symposium on Microarchitecture (MICRO)","author":"Yang J.","year":"2002","unstructured":"J. Yang and R. Gupta , \" Energy efficient frequent value data cache design,\" in IEEE\/ACM 35th International Symposium on Microarchitecture (MICRO) , pp. 197 -- 207 , nov. 2002 . J. Yang and R. Gupta, \"Energy efficient frequent value data cache design,\" in IEEE\/ACM 35th International Symposium on Microarchitecture (MICRO), pp. 197--207, nov. 2002."}],"event":{"name":"ISLPED04: International Symposium on Low Power Electronics and Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Newport Beach California USA","acronym":"ISLPED04"},"container-title":["Proceedings of the 2004 international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013271","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1013235.1013271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:14Z","timestamp":1750264274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013271"}},"subtitle":["a low-power L2 cache system"],"short-title":[],"issued":{"date-parts":[[2004,8,9]]},"references-count":26,"alternative-id":["10.1145\/1013235.1013271","10.1145\/1013235"],"URL":"https:\/\/doi.org\/10.1145\/1013235.1013271","relation":{},"subject":[],"published":{"date-parts":[[2004,8,9]]},"assertion":[{"value":"2004-08-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}