{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:38Z","timestamp":1750308218501,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,8,9]],"date-time":"2004-08-09T00:00:00Z","timestamp":1092009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,8,9]]},"DOI":"10.1145\/1013235.1013277","type":"proceedings-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T17:39:48Z","timestamp":1097170788000},"page":"150-155","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Active mode leakage reduction using fine-grained forward body biasing strategy"],"prefix":"10.1145","author":[{"given":"Vishal","family":"Khandelwal","sequence":"first","affiliation":[{"name":"University of Maryland at College Park"}]},{"given":"Ankur","family":"Srivastava","sequence":"additional","affiliation":[{"name":"University of Maryland at College Park"}]}],"member":"320","published-online":{"date-parts":[[2004,8,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337549"},{"key":"e_1_3_2_1_2_1","first-page":"359","volume-title":"ASIC\/SOC Conference","author":"Bhavnagarwala A. J.","year":"2000","unstructured":"A. J. Bhavnagarwala CMOS SRAM Cells for Fast , Portable Applications\". In ASIC\/SOC Conference , pages 359 -- 363 , 2000 . A. J. Bhavnagarwala et al. \"Dynamic-Threshold CMOS SRAM Cells for Fast, Portable Applications\". In ASIC\/SOC Conference, pages 359--363, 2000."},{"key":"e_1_3_2_1_3_1","volume-title":"Microelectronic Circuits","author":"Sedra A.","year":"1997","unstructured":"A. Sedra and K. Smith . \" Microelectronic Circuits \". Oxford University Press , 1997 . A. Sedra and K. Smith. \"Microelectronic Circuits\". Oxford University Press, 1997."},{"key":"e_1_3_2_1_4_1","first-page":"312","volume-title":"VLSI Circuits Symp.","year":"2002","unstructured":"Ali Keshavarzi et al. \"Forward body Bias for Microprocessors in 130nm Technology Generation and Beyond \". In VLSI Circuits Symp. , pages 312 -- 315 , 2002 . Ali Keshavarzi et al. \"Forward body Bias for Microprocessors in 130nm Technology Generation and Beyond\". In VLSI Circuits Symp., pages 312--315, 2002."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566473"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871511"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/96559.96597"},{"key":"e_1_3_2_1_8_1","volume-title":"Department of EECS. UC Berkeley","author":"Sentovich E.M.","year":"1992","unstructured":"E.M. Sentovich , K.J. Singh , L. Lavagno , C. Moon , R. Murgai , A. Saldanha , H. Savoj , P.R. Stephan , R.K. Brayton , A.L. Sangiovanni-Vincentelli . SIS : A System for Sequential Circuit Synthesis. Memorandum No. UCB\/ERL M92\/41 , Department of EECS. UC Berkeley , May 1992 . E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB\/ERL M92\/41, Department of EECS. UC Berkeley, May 1992."},{"key":"e_1_3_2_1_9_1","first-page":"140","volume-title":"VLSI Circuits Symp.","author":"Kawaguchi H.","year":"1998","unstructured":"H. Kawaguchi In VLSI Circuits Symp. , pages 140 -- 141 , 1998 . H. Kawaguchi et al. \"Dynamic Leakage Cut-Off Scheme for Low-Voltage SRAM's\". In VLSI Circuits Symp., pages 140--141, 1998."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.509853"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871549"},{"key":"e_1_3_2_1_12_1","volume-title":"ISSCC","author":"Narendra S.","year":"2002","unstructured":"S. Narendra \" 1.1V 1GHz Communications Router with On-Chip Body Bias in 150nm CMOS \". In ISSCC , 2002 . S. Narendra et al. \"1.1V 1GHz Communications Router with On-Chip Body Bias in 150nm CMOS\". In ISSCC, 2002."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.75219"},{"key":"e_1_3_2_1_14_1","first-page":"789","volume-title":"IEDM","author":"Taur Y.","year":"1998","unstructured":"Y. Taur \" 25 nm CMOS Design Considerations \". In IEDM , pages 789 -- 792 , 1998 . Y. Taur et al. \"25 nm CMOS Design Considerations\". In IEDM, pages 789--792, 1998."}],"event":{"name":"ISLPED04: International Symposium on Low Power Electronics and Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Newport Beach California USA","acronym":"ISLPED04"},"container-title":["Proceedings of the 2004 international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013277","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1013235.1013277","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:14Z","timestamp":1750264274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013277"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,8,9]]},"references-count":14,"alternative-id":["10.1145\/1013235.1013277","10.1145\/1013235"],"URL":"https:\/\/doi.org\/10.1145\/1013235.1013277","relation":{},"subject":[],"published":{"date-parts":[[2004,8,9]]},"assertion":[{"value":"2004-08-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}