{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:57:11Z","timestamp":1759147031278,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,8,9]],"date-time":"2004-08-09T00:00:00Z","timestamp":1092009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,8,9]]},"DOI":"10.1145\/1013235.1013298","type":"proceedings-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T17:39:48Z","timestamp":1097170788000},"page":"248-251","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies"],"prefix":"10.1145","author":[{"given":"Bhaskar","family":"Chatterjee","sequence":"first","affiliation":[{"name":"University of Waterloo, Waterloo, ON, Canada"}]},{"given":"Manoj","family":"Sachdev","sequence":"additional","affiliation":[{"name":"University of Waterloo, Waterloo, ON, Canada"}]},{"given":"Ram","family":"Krishnamurthy","sequence":"additional","affiliation":[{"name":"Intel Corp., Hillsboro, OR"}]}],"member":"320","published-online":{"date-parts":[[2004,8,9]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Semiconductor Industry Associations \"International Technology Roadmap for Semiconductors 2001Edition\" 2001.  Semiconductor Industry Associations \"International Technology Roadmap for Semiconductors 2001Edition\" 2001."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","DOI":"10.1109\/9780470544365","volume-title":"Design of High Performance Microprocessor Circuits","author":"Chandrakasan A.","year":"2000","unstructured":"A. Chandrakasan , W.J. Bowhill , and F. Fox , Design of High Performance Microprocessor Circuits . IEEE Press , Piscataway, N.J. , 2000 . A. Chandrakasan, W.J. Bowhill, and F. Fox, Design of High Performance Microprocessor Circuits. IEEE Press, Piscataway, N.J., 2000."},{"key":"e_1_3_2_1_3_1","first-page":"428","volume-title":"12th IEEE Intl. Conf. on VLSI Design","author":"Stan M. R.","year":"1999","unstructured":"M. R. Stan , \"Optimal Voltages and Sizing for Low Power,\" 12th IEEE Intl. Conf. on VLSI Design , pp. 428 -- 433 , 1999 . M. R. Stan, \"Optimal Voltages and Sizing for Low Power,\" 12th IEEE Intl. Conf. on VLSI Design, pp. 428--433, 1999."},{"key":"e_1_3_2_1_4_1","first-page":"227","volume-title":"ICCD","author":"Sirisantana N.","year":"2000","unstructured":"N. Sirisantana , L. Wei , and K. Roy , \" High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness,\" Proc . ICCD , pp. 227 -- 232 , 2000 . N. Sirisantana, L. Wei, and K. Roy, \"High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness,\" Proc. ICCD, pp. 227--232, 2000."},{"key":"e_1_3_2_1_5_1","first-page":"6","volume-title":"Intl Conf. on Microprocessors and Nanotechnology","author":"Kuroda T.","year":"2001","unstructured":"T. Kuroda , \" CMOS Design Challenges to Power Wall,\" Intl Conf. on Microprocessors and Nanotechnology , pp. 6 -- 7 , 2001 . T. Kuroda, \"CMOS Design Challenges to Power Wall,\" Intl Conf. on Microprocessors and Nanotechnology, pp. 6--7, 2001."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/263272.263273"},{"issue":"11","key":"e_1_3_2_1_7_1","first-page":"1770","article-title":"al, \"A 0.9V, 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme","volume":"31","author":"Kuroda T.","unstructured":"T. Kuroda , et. al, \"A 0.9V, 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme ,\" IEEE JSSC , vol. 31 , no. 11 , pp. 1770 -- 1779 , Nov. 96. T. Kuroda, et. al, \"A 0.9V, 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme,\" IEEE JSSC, vol. 31, no. 11, pp. 1770--1779, Nov. 96.","journal-title":"IEEE JSSC"},{"key":"e_1_3_2_1_8_1","unstructured":"http:\/\/www-device.eecs.berkeley.edu\/~ptm: BSIM3 files  http:\/\/www-device.eecs.berkeley.edu\/~ptm: BSIM3 files"},{"key":"e_1_3_2_1_9_1","first-page":"201","article-title":"New paradigm of predictive MOSFET and interconnect modeling for early circuit design","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , T. Sato , D. Sylvester , M. Orshansky , and C. Hu , \" New paradigm of predictive MOSFET and interconnect modeling for early circuit design ,\" Proc. of IEEE CICC , pp. 201 -- 204 , Jun. 2000 . Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, \"New paradigm of predictive MOSFET and interconnect modeling for early circuit design,\" Proc. of IEEE CICC, pp. 201--204, Jun. 2000.","journal-title":"Proc. of IEEE CICC"},{"key":"e_1_3_2_1_10_1","first-page":"1636","volume-title":"IEEE JSSC","volume":"36","author":"Matthew S.","year":"2001","unstructured":"S. Matthew , R. Krishnamurthy , M. Anders , R. Rios , K. Mistry , and K. Soumyanath , \" Sub-500ps 64-b ALUs in 0.18mm SOI\/Bulk CMOS: Design and Scaling Trends \", IEEE JSSC , vol. 36 , no.-11, pp. 1636 -- 1646 , Nov. 2001 . S. Matthew, R. Krishnamurthy, M. Anders, R. Rios, K. Mistry, and K. Soumyanath, \"Sub-500ps 64-b ALUs in 0.18mm SOI\/Bulk CMOS: Design and Scaling Trends\", IEEE JSSC, vol. 36, no.-11, pp. 1636--1646, Nov. 2001."},{"key":"e_1_3_2_1_11_1","first-page":"128","volume-title":"Symp. on VLSI Circuits","author":"Krishnamurthy R.","year":"2002","unstructured":"R. Krishnamurthy , S. Hsu , M. Anders , B. Bloechel , B. Chatterjee , M. Sachdev , and S. Borkar , \" Dual supply voltage clocking for 5GHz 130nm integer execution core \", Symp. on VLSI Circuits , pp. 128 -- 129 , 2002 . R. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, and S. Borkar, \"Dual supply voltage clocking for 5GHz 130nm integer execution core\", Symp. on VLSI Circuits, pp. 128--129, 2002."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871538"}],"event":{"name":"ISLPED04: International Symposium on Low Power Electronics and Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Newport Beach California USA","acronym":"ISLPED04"},"container-title":["Proceedings of the 2004 international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013298","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1013235.1013298","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:14Z","timestamp":1750264274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013298"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,8,9]]},"references-count":12,"alternative-id":["10.1145\/1013235.1013298","10.1145\/1013235"],"URL":"https:\/\/doi.org\/10.1145\/1013235.1013298","relation":{},"subject":[],"published":{"date-parts":[[2004,8,9]]},"assertion":[{"value":"2004-08-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}