{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T10:11:09Z","timestamp":1773655869393,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,8,9]],"date-time":"2004-08-09T00:00:00Z","timestamp":1092009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,8,9]]},"DOI":"10.1145\/1013235.1013318","type":"proceedings-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T17:39:48Z","timestamp":1097170788000},"page":"344-349","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Application adaptive energy efficient clustered architectures"],"prefix":"10.1145","author":[{"given":"Diana","family":"Marculescu","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,8,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774601"},{"key":"e_1_3_2_1_2_1","first-page":"158","volume-title":"Intl. Symp. on Computer Architecture (ISCA)","author":"Iyer A.","year":"2002"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/874076.876477"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_5_1","first-page":"356","volume-title":"Intl. Symposium on Microarchitecture (MICRO)","author":"Semeraro G.","year":"2002"},{"key":"e_1_3_2_1_6_1","unstructured":"D. M. Chapiro \"Globally-Asynchronous Locally-Synchronous Systems\" PhD Thesis Stanford University Oct. 1984. D. M. Chapiro \"Globally-Asynchronous Locally-Synchronous Systems\" PhD Thesis Stanford University Oct. 1984."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310091"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774629"},{"key":"e_1_3_2_1_9_1","volume-title":"Kool Chips Workshop, in conjunction with MICRO","author":"Casmira J.","year":"2000"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379253"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876440"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545222"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/645989.674310"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612245"},{"key":"e_1_3_2_1_15_1","first-page":"Q1","author":"Hinton G.","year":"2001","journal-title":"\"The Microarchitecture of the Pentium4 Processor,\" in Intel Technology Journal"},{"key":"e_1_3_2_1_16_1","first-page":"188","volume-title":"1998 IEEE Intl. Conference on Computer Design (ICCD'98)","author":"Kol R.","year":"1998"},{"key":"e_1_3_2_1_17_1","first-page":"307","volume-title":"Proc. Intl. Conference on Computer Design (ICCD), IEEE Computer Society Press","author":"Bormann D. S.","year":"1997"},{"key":"e_1_3_2_1_18_1","first-page":"87","volume-title":"Proc. Intl. Symposium on Advanced Research in Asynchronous Circuits and Systems","author":"Seizovic J.","year":"1994"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"T. Chelcea and S. M. Nowick \"A Low-Latency FIFO for Mixed-Clock Systems \" in Proc. of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00) pp. 119--126 April 2000. T. Chelcea and S. M. Nowick \"A Low-Latency FIFO for Mixed-Clock Systems \" in Proc. of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00) pp. 119--126 April 2000.","DOI":"10.1109\/IWV.2000.844540"},{"key":"e_1_3_2_1_20_1","first-page":"114","volume-title":"Intl. Symposium on Microarchitecture (MICRO-34)","author":"Seng J.","year":"2001"},{"key":"e_1_3_2_1_21_1","first-page":"160","volume-title":"Conf. on Parallel Architectures and Compilation Techniques (PACT'99)","author":"Canal R.","year":"1999"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.335008"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"}],"event":{"name":"ISLPED04: International Symposium on Low Power Electronics and Design","location":"Newport Beach California USA","acronym":"ISLPED04","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2004 international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013318","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1013235.1013318","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:14Z","timestamp":1750264274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1013235.1013318"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,8,9]]},"references-count":23,"alternative-id":["10.1145\/1013235.1013318","10.1145\/1013235"],"URL":"https:\/\/doi.org\/10.1145\/1013235.1013318","relation":{},"subject":[],"published":{"date-parts":[[2004,8,9]]},"assertion":[{"value":"2004-08-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}