{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:31Z","timestamp":1750308211397,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,9,4]],"date-time":"2004-09-04T00:00:00Z","timestamp":1094256000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,9,4]]},"DOI":"10.1145\/1016568.1016620","type":"proceedings-article","created":{"date-parts":[[2005,1,30]],"date-time":"2005-01-30T17:55:16Z","timestamp":1107107716000},"page":"186-191","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A programmable cellular neural network circuit"],"prefix":"10.1145","author":[{"given":"Michel","family":"Leong","sequence":"first","affiliation":[{"name":"Instituto Superior T\u00e9cnico \/ INESC-ID Lisboa, Lisboa, Portugal"}]},{"given":"Pedro","family":"Vasconcelos","sequence":"additional","affiliation":[{"name":"Instituto Superior T\u00e9cnico \/ INESC-ID Lisboa, Lisboa, Portugal"}]},{"given":"Jorge R.","family":"Fernandes","sequence":"additional","affiliation":[{"name":"Instituto Superior T\u00e9cnico \/ INESC-ID Lisboa, Lisboa, Portugal"}]},{"given":"Leonel","family":"Sousa","sequence":"additional","affiliation":[{"name":"Instituto Superior T\u00e9cnico \/ INESC-ID Lisboa, Lisboa, Portugal"}]}],"member":"320","published-online":{"date-parts":[[2004,9,4]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"35","article-title":"Cellular neural networks: Theory","author":"Chua L. O.","year":"1988","unstructured":"L. O. Chua and L. Yang , \" Cellular neural networks: Theory ,\" IEEE Trans. Circuits Syst. , vol. C AS- 35 , pp. 1257--1274, October 1988 . L. O. Chua and L. Yang, \"Cellular neural networks: Theory,\" IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1257--1274, October 1988.","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_3_2_1_2_1","first-page":"35","article-title":"Cellular neural networks: Applications","author":"Chua L. O.","year":"1988","unstructured":"L. O. Chua and L. Yang , \" Cellular neural networks: Applications ,\" IEEE Trans. Circuits Syst. , vol. C AS- 35 , pp. 1275--1290, October 1988 . L. O. Chua and L. Yang, \"Cellular neural networks: Applications,\" IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1275--1290, October 1988.","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_3_2_1_3_1","unstructured":"M. Hanggi \"Cellular Neural Network Simulator\" http:\/\/www.isi.ee.ethz.ch\/~haenggi\/CNNsim.html 2001.  M. Hanggi \"Cellular Neural Network Simulator\" http:\/\/www.isi.ee.ethz.ch\/~haenggi\/CNNsim.html 2001."},{"key":"e_1_3_2_1_4_1","volume-title":"Microelectronic Circuits","author":"Sedra A.","year":"1991","unstructured":"A. Sedra and K. Smith , Microelectronic Circuits , 3 rd Edition, Saunders College Publishing , 1991 . A.Sedra and K.Smith, Microelectronic Circuits, 3rd Edition, Saunders College Publishing, 1991.","edition":"3"},{"key":"e_1_3_2_1_5_1","unstructured":"M. Valle and F. Diotalevi \"An analog CMOS four quadrant current-mode Multiplier for low power artificial neural networks implementation\" Dep. of Biophysical and Electronic Engineering Univ. of Genova.  M. Valle and F. Diotalevi \"An analog CMOS four quadrant current-mode Multiplier for low power artificial neural networks implementation\" Dep. of Biophysical and Electronic Engineering Univ. of Genova."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.222820"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.678895"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.104189"},{"key":"e_1_3_2_1_9_1","unstructured":"J. Vital A. Marques P. Azevedo and J. Franca \"Design Considerations for a Retargetable 12b 200MHz CMOS Current-Steering DAC\" ChipIdea-Microelectr\u00f3nica S.A.  J. Vital A. Marques P. Azevedo and J. Franca \"Design Considerations for a Retargetable 12b 200MHz CMOS Current-Steering DAC\" ChipIdea-Microelectr\u00f3nica S.A."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.735536"}],"event":{"name":"SBCCI04: 17th Symposium on Integrated Circuits and System Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Pernambuco Brazil","acronym":"SBCCI04"},"container-title":["Proceedings of the 17th symposium on Integrated circuits and system design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1016568.1016620","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1016568.1016620","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:04Z","timestamp":1750264264000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1016568.1016620"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,9,4]]},"references-count":10,"alternative-id":["10.1145\/1016568.1016620","10.1145\/1016568"],"URL":"https:\/\/doi.org\/10.1145\/1016568.1016620","relation":{},"subject":[],"published":{"date-parts":[[2004,9,4]]},"assertion":[{"value":"2004-09-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}