{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:21:04Z","timestamp":1780356064611,"version":"3.54.1"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2004,9,1]],"date-time":"2004-09-01T00:00:00Z","timestamp":1093996800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2004,9]]},"abstract":"<jats:p>\n            We observe that the challenges software optimizers and microarchitects face every day boil down to a single problem: bottleneck analysis. A bottleneck is any event or resource that contributes to execution time, such as a critical cache miss or window stall. Tasks such as tuning processors for energy efficiency and finding the right loads to prefetch all require measuring the performance costs of bottlenecks.In the past, simple event counts were enough to find the important bottlenecks. Today, the parallelism of modern processors makes such analysis much more difficult, rendering traditional performance counters less useful. If two microarchitectural events (such as a fetch stall and a cache miss) occur in the same cycle, which event should we blame for the cycle? What cost should we assign to each event? In this paper, we introduce a new model for understanding event costs to facilitate processor design and optimization.First, we observe that all instructions, hardware structures, and events in a machine can interact in only one of two ways (in parallel or serially). We quantify these interactions by defining\n            <jats:italic>interaction cost<\/jats:italic>\n            , which can be zero (independent, no interaction), positive (parallel), or negative (serial).Second, we illustrate the value of using interaction costs in processor design and optimization. In a processor with a long pipeline, we show how to mitigate the negative performance effect of long latency \"critical\" loops, such as the level-one cache access and issue-wakeup, by optimizing seemingly unrelated resources that\n            <jats:italic>interact<\/jats:italic>\n            with them.Finally, we propose\n            <jats:italic>shotgun profiling<\/jats:italic>\n            , a class of hardware profiling infrastructures that are parallelism-aware, in contrast to traditional event counters. Our recommended design requires only modest extensions to current hardware counters, while enabling the construction of full-featured dependence graphs of the microexecution. With these dependence graphs, many types of analyses can be performed, including identifying critical instructions, finding slack, as well as computing costs and interaction costs.\n          <\/jats:p>","DOI":"10.1145\/1022969.1022971","type":"journal-article","created":{"date-parts":[[2005,8,1]],"date-time":"2005-08-01T17:31:42Z","timestamp":1122917502000},"page":"272-304","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":37,"title":["Interaction cost and shotgun profiling"],"prefix":"10.1145","volume":"1","author":[{"given":"Brian A.","family":"Fields","sequence":"first","affiliation":[{"name":"University of California, Berkeley, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rastislav","family":"Bodik","sequence":"additional","affiliation":[{"name":"University of California, Berkeley, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mark D.","family":"Hill","sequence":"additional","affiliation":[{"name":"University of Wisconsin, Madison, WI"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chris J.","family":"Newburn","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2004,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Anderson J. M. Berc L. M. Dean J. Ghemawat S. Henzinger M. R. Leung S. A. Sites R. L. Vandevoorde M. T. Waldspurger C. A. and Weihl W. E. 1997. Continuous profiling: Where have all the cycles gone? ACM Trans. Comput. Syst. 10.1145\/265924.265925   Anderson J. M. Berc L. M. Dean J. Ghemawat S. Henzinger M. R. Leung S. A. Sites R. L. Vandevoorde M. T. Waldspurger C. A. and Weihl W. E. 1997. Continuous profiling: Where have all the cycles gone? ACM Trans. Comput. Syst. 10.1145\/265924.265925","DOI":"10.1145\/268998.266637"},{"key":"e_1_2_1_2_1","volume-title":"28th International Symposium on Computer Architecture. 10","author":"Bahar R. I.","unstructured":"Bahar , R. I. and Manne , S . 2001. Power and energy reduction via pipeline balancing . In 28th International Symposium on Computer Architecture. 10 .1145\/379240.379265 Bahar, R. I. and Manne, S. 2001. Power and energy reduction via pipeline balancing. In 28th International Symposium on Computer Architecture. 10.1145\/379240.379265"},{"key":"e_1_2_1_3_1","volume-title":"8th International Symposium on High-Performance Computer Architecture.","author":"Borch E.","unstructured":"Borch , E. , Tune , E. , Manne , B. , and Emer , J . 2002. Loose loops sink chips . In 8th International Symposium on High-Performance Computer Architecture. Borch, E., Tune, E., Manne, B., and Emer, J. 2002. Loose loops sink chips. In 8th International Symposium on High-Performance Computer Architecture."},{"key":"e_1_2_1_4_1","volume-title":"20th International Symposium on Computer Architecture. 10","author":"Boyd E. L.","unstructured":"Boyd , E. L. and Davidson , E. S . 1993. Hierarchical performance modeling with MACS: A case study of the Convex C-240 . In 20th International Symposium on Computer Architecture. 10 .1145\/165123.165155 Boyd, E. L. and Davidson, E. S. 1993. Hierarchical performance modeling with MACS: A case study of the Convex C-240. In 20th International Symposium on Computer Architecture. 10.1145\/165123.165155"},{"key":"e_1_2_1_5_1","unstructured":"Burger D. C. and Austin T. M. 1997. The Simplescalar Tool Set version 2.0. Tech. Rep. CS-TR-1997--1342 University of Wisconsin Madison.  Burger D. C. and Austin T. M. 1997. The Simplescalar Tool Set version 2.0. Tech. Rep. CS-TR-1997--1342 University of Wisconsin Madison."},{"key":"e_1_2_1_6_1","volume-title":"26th International Symposium on Computer Architecture. 10","author":"Calder B.","unstructured":"Calder , B. , Reinman , G. , and Tullsen , D . 1999. Selective value prediction . In 26th International Symposium on Computer Architecture. 10 .1145\/300979.300985 Calder, B., Reinman, G., and Tullsen, D. 1999. Selective value prediction. In 26th International Symposium on Computer Architecture. 10.1145\/300979.300985"},{"key":"e_1_2_1_7_1","volume-title":"Kool Chips Workshop in Conjunction with MICRO 33","author":"Casmira J.","unstructured":"Casmira , J. and Grunwald , D . 2000. Dynamic instruction scheduling slack . In Kool Chips Workshop in Conjunction with MICRO 33 . Casmira, J. and Grunwald, D. 2000. Dynamic instruction scheduling slack. In Kool Chips Workshop in Conjunction with MICRO 33."},{"key":"e_1_2_1_8_1","volume-title":"28th International Symposium on Computer Architecture. 10","author":"Collins J. D.","unstructured":"Collins , J. D. , Wang , H. , Tullsen , D. M. , Hughes , C. , Lee , Y. , Lavery , D. , and Shen , J. P . 2001. Speculative precomputation: Long-range prefetching of delinquent loads . In 28th International Symposium on Computer Architecture. 10 .1145\/379240.379248 Collins, J. D., Wang, H., Tullsen, D. M., Hughes, C., Lee, Y., Lavery, D., and Shen, J. P. 2001. Speculative precomputation: Long-range prefetching of delinquent loads. In 28th International Symposium on Computer Architecture. 10.1145\/379240.379248"},{"key":"e_1_2_1_9_1","volume-title":"30th International Symposium on Microarchitecture.","author":"Dean J.","unstructured":"Dean , J. , Hicks , J. E. , Waldspurger , C. A. , Weihl , W. E. , and Chrysos , G . 1997. ProfileMe: Hardware support for instruction-level profiling on out-of-order processors . In 30th International Symposium on Microarchitecture. Dean, J., Hicks, J. E., Waldspurger, C. A., Weihl, W. E., and Chrysos, G. 1997. ProfileMe: Hardware support for instruction-level profiling on out-of-order processors. In 30th International Symposium on Microarchitecture."},{"key":"e_1_2_1_10_1","volume-title":"34th International Symposium on Microarchitecture.","author":"Fahs B.","unstructured":"Fahs , B. , Bose , S. , Crum , M. , Slechta , B. , Spadini , F. , Tung , T. , Patel , S. J. , and Lumetta , S. S . 2001. Performance characterization of a hardware mechanism for dynamic optimization . In 34th International Symposium on Microarchitecture. Fahs, B., Bose, S., Crum, M., Slechta, B., Spadini, F., Tung, T., Patel, S. J., and Lumetta, S. S. 2001. Performance characterization of a hardware mechanism for dynamic optimization. In 34th International Symposium on Microarchitecture."},{"key":"e_1_2_1_11_1","volume-title":"29th International Symposium on Computer Architecture.","author":"Fields B.","unstructured":"Fields , B. , Bod\u00edk , R. , and Hill , M. D . 2002. Slack: Maximizing performance under technological constraints . In 29th International Symposium on Computer Architecture. Fields, B., Bod\u00edk, R., and Hill, M. D. 2002. Slack: Maximizing performance under technological constraints. In 29th International Symposium on Computer Architecture."},{"key":"e_1_2_1_12_1","volume-title":"28th International Symposium on Computer Architecture. 10","author":"Fields B.","unstructured":"Fields , B. , Rubin , S. , and Bod\u00edk , R . 2001. Focusing processor policies via critical-path prediction . In 28th International Symposium on Computer Architecture. 10 .1145\/379240.379253 Fields, B., Rubin, S., and Bod\u00edk, R. 2001. Focusing processor policies via critical-path prediction. In 28th International Symposium on Computer Architecture. 10.1145\/379240.379253"},{"key":"e_1_2_1_13_1","unstructured":"Fisk B. R. and Bahar R. I. 1999. The non-critical buffer: Using load latency tolerance to improve data cache efficiency.  Fisk B. R. and Bahar R. I. 1999. The non-critical buffer: Using load latency tolerance to improve data cache efficiency."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.7542800"},{"key":"e_1_2_1_15_1","volume-title":"29th International Symposium on Computer Architecture.","author":"Hartstein A.","unstructured":"Hartstein , A. and Puzak , T. R . 2002. The optimum pipeline depth for a microprocessor . In 29th International Symposium on Computer Architecture. Hartstein, A. and Puzak, T. R. 2002. The optimum pipeline depth for a microprocessor. In 29th International Symposium on Computer Architecture."},{"key":"e_1_2_1_16_1","volume-title":"Computer Architecture: A Quantitative Approach, 3 rd ed","author":"Hennessy J. L.","year":"2002","unstructured":"Hennessy , J. L. and Patterson , D. A . 2002 . Computer Architecture: A Quantitative Approach, 3 rd ed . Morgan Kaufmann Publishers , Los Altos, CA . Hennessy, J. L. and Patterson, D. A. 2002. Computer Architecture: A Quantitative Approach, 3 rd ed. Morgan Kaufmann Publishers, Los Altos, CA."},{"key":"e_1_2_1_17_1","volume-title":"29th International Symposium on Computer Architecture.","author":"Hrishikesh M. S.","unstructured":"Hrishikesh , M. S. , Jouppi , N. P. , Farkas , K. I. , Burger , D. , Keckler , S. W. , and Shivakumar , P . 2002. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays . In 29th International Symposium on Computer Architecture. Hrishikesh, M. S., Jouppi, N. P., Farkas, K. I., Burger, D., Keckler, S. W., and Shivakumar, P. 2002. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. In 29th International Symposium on Computer Architecture."},{"key":"e_1_2_1_18_1","unstructured":"Intel. 2003. Intel Pentium 4 Processor Manual. Available at http:\/\/developer.intel.com\/design\/ pentium4\/manuals\/.  Intel. 2003. Intel Pentium 4 Processor Manual. Available at http:\/\/developer.intel.com\/design\/ pentium4\/manuals\/."},{"key":"e_1_2_1_19_1","volume-title":"The Art of Computer Systems Performance Analysis","author":"Jain R.","unstructured":"Jain , R. 1991. The Art of Computer Systems Performance Analysis . Wiley Professional Computing . Jain, R. 1991. The Art of Computer Systems Performance Analysis. Wiley Professional Computing."},{"key":"e_1_2_1_20_1","volume-title":"31st International Symposium on Computer Architecture.","author":"Karkhanis T.","unstructured":"Karkhanis , T. and Smith , J. E . 2004. A first-order superscalar processor model . In 31st International Symposium on Computer Architecture. Karkhanis, T. and Smith, J. E. 2004. A first-order superscalar processor model. In 31st International Symposium on Computer Architecture."},{"key":"e_1_2_1_21_1","volume-title":"29th International Symposium on Microarchitecture.","author":"Lipasti M. H.","unstructured":"Lipasti , M. H. and Shen , J. P . 1996. Exceeding the dataflow limit via value prediction . In 29th International Symposium on Microarchitecture. Lipasti, M. H. and Shen, J. P. 1996. Exceeding the dataflow limit via value prediction. In 29th International Symposium on Microarchitecture."},{"key":"e_1_2_1_22_1","volume-title":"3rd International Symposium on High Performance Computer Architecture.","author":"Pai V. S.","unstructured":"Pai , V. S. , Ranganathan , P. , and Adve , S. V . 1997. The impact of instruction-level parallelism on multiprocessor performance and simulation methodology . In 3rd International Symposium on High Performance Computer Architecture. Pai, V. S., Ranganathan, P., and Adve, S. V. 1997. The impact of instruction-level parallelism on multiprocessor performance and simulation methodology. In 3rd International Symposium on High Performance Computer Architecture."},{"key":"e_1_2_1_23_1","volume-title":"25th International Symposium on Computer Architecture. 10","author":"Patel S.","unstructured":"Patel , S. , Evers , M. , and Patt , Y . 1998. Improving trace cache effectiveness with branch promotion and trace packing . In 25th International Symposium on Computer Architecture. 10 .1145\/279358.279394 Patel, S., Evers, M., and Patt, Y. 1998. Improving trace cache effectiveness with branch promotion and trace packing. In 25th International Symposium on Computer Architecture. 10.1145\/279358.279394"},{"key":"e_1_2_1_24_1","volume-title":"34th International Symposium on Microarchitecture.","author":"Rajwar R.","unstructured":"Rajwar , R. and Goodman , J. R . 2001. Speculative lock elision: Enabling highly concurrent multithreaded execution . In 34th International Symposium on Microarchitecture. Rajwar, R. and Goodman, J. R. 2001. Speculative lock elision: Enabling highly concurrent multithreaded execution. In 34th International Symposium on Microarchitecture."},{"key":"e_1_2_1_25_1","volume-title":"8th International Symposium on High-Performance Computer Architecture.","author":"Rakvic R.","unstructured":"Rakvic , R. , Black , B. , Limaye , D. , and Shen , J. P . 2002. Non-vital loads . In 8th International Symposium on High-Performance Computer Architecture. Rakvic, R., Black, B., Limaye, D., and Shen, J. P. 2002. Non-vital loads. In 8th International Symposium on High-Performance Computer Architecture."},{"key":"e_1_2_1_26_1","doi-asserted-by":"crossref","unstructured":"Ranganathan P. Gharachorloo K. Adve S. V. and Barroso L. A. 1998. Performance of database workloads on shared-memory systems with out-of-order processors.  Ranganathan P. Gharachorloo K. Adve S. V. and Barroso L. A. 1998. Performance of database workloads on shared-memory systems with out-of-order processors.","DOI":"10.1145\/291069.291067"},{"key":"e_1_2_1_27_1","volume-title":"15th Symposium on Operating Systems Principles. 10","author":"Rosenblum M.","unstructured":"Rosenblum , M. , Bugnion , E. , Herrod , S. A. , Witchel , E. , and Gupta , A . 1995. The impact of architectural trends on operating system performance . In 15th Symposium on Operating Systems Principles. 10 .1145\/224056.224078 Rosenblum, M., Bugnion, E., Herrod, S. A., Witchel, E., and Gupta, A. 1995. The impact of architectural trends on operating system performance. In 15th Symposium on Operating Systems Principles. 10.1145\/224056.224078"},{"key":"e_1_2_1_28_1","volume-title":"Tech. Rep. CS-TR-2000-1411","author":"Roth A.","year":"2000","unstructured":"Roth , A. and Sohi , G . 2000 . Speculative Data-Driven Sequencing for Imperative Programs. Tech. Rep. CS-TR-2000-1411 , University of Wisconsin, Madison . Roth, A. and Sohi, G. 2000. Speculative Data-Driven Sequencing for Imperative Programs. Tech. Rep. CS-TR-2000-1411, University of Wisconsin, Madison."},{"key":"e_1_2_1_29_1","volume-title":"10th International Conference on Architectural Support for Programming Languages and Operating Systems. 10","author":"Sasanka R.","unstructured":"Sasanka , R. , Hughes , C. J. , and Adve , S. V . 2002. Joint local and global hardware adaptations for energy . In 10th International Conference on Architectural Support for Programming Languages and Operating Systems. 10 .1145\/605397.605413 Sasanka, R., Hughes, C. J., and Adve, S. V. 2002. Joint local and global hardware adaptations for energy. In 10th International Conference on Architectural Support for Programming Languages and Operating Systems. 10.1145\/605397.605413"},{"key":"e_1_2_1_30_1","volume-title":"8th International Symposium on High-Performance Computer Architecture.","author":"Semeraro G.","unstructured":"Semeraro , G. , Magklis , G. , Balasubramonian , R. , Albonesi , D. , Dwarkadas , S. , and Scott , M . 2002. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling . In 8th International Symposium on High-Performance Computer Architecture. Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D., Dwarkadas, S., and Scott, M. 2002. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In 8th International Symposium on High-Performance Computer Architecture."},{"key":"e_1_2_1_31_1","volume-title":"34th International Symposium on Microarchitecture.","author":"Seng J. S.","unstructured":"Seng , J. S. , Tune , E. S. , and Tullsen , D. M . 2001. Reducing power with dynamic critical path information . In 34th International Symposium on Microarchitecture. Seng, J. S., Tune, E. S., and Tullsen, D. M. 2001. Reducing power with dynamic critical path information. In 34th International Symposium on Microarchitecture."},{"key":"e_1_2_1_32_1","volume-title":"24th International Symposium on Computer Architecture. 10","author":"Sodani A.","unstructured":"Sodani , A. and Sohi , G. S . 1997. Dynamic instruction reuse . In 24th International Symposium on Computer Architecture. 10 .1145\/264107.264200 Sodani, A. and Sohi, G. S. 1997. Dynamic instruction reuse. In 24th International Symposium on Computer Architecture. 10.1145\/264107.264200"},{"key":"e_1_2_1_33_1","volume-title":"29th International Symposium on Computer Architecture.","author":"Sprangle E.","unstructured":"Sprangle , E. and Carmean , D . 2002. Increasing processor performance by implementing deeper pipelines . In 29th International Symposium on Computer Architecture. Sprangle, E. and Carmean, D. 2002. Increasing processor performance by implementing deeper pipelines. In 29th International Symposium on Computer Architecture."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1028478"},{"key":"e_1_2_1_35_1","volume-title":"28th International Symposium on Computer Architecture. 10","author":"Srinivasan S. T.","unstructured":"Srinivasan , S. T. , ching Ju , R. D. , Lebeck , A. R. , and Wilkerson , C . 2001. Locality vs. criticality . In 28th International Symposium on Computer Architecture. 10 .1145\/379240.379258 Srinivasan, S. T., ching Ju, R. D., Lebeck, A. R., and Wilkerson, C. 2001. Locality vs. criticality. In 28th International Symposium on Computer Architecture. 10.1145\/379240.379258"},{"key":"e_1_2_1_36_1","volume-title":"31st International Symposium on Microarchitecture.","author":"Srinivasan S. T.","unstructured":"Srinivasan , S. T. and Lebeck , A. R . 1998. Load latency tolerance in dynamically scheduled processors . In 31st International Symposium on Microarchitecture. Srinivasan, S. T. and Lebeck, A. R. 1998. Load latency tolerance in dynamically scheduled processors. In 31st International Symposium on Microarchitecture."},{"key":"e_1_2_1_37_1","volume-title":"27th International Symposium on Computer Architecture. 10","author":"Steffan J. G.","unstructured":"Steffan , J. G. , Colohan , C. B. , Zhai , A. , and Mowry , T. C . 2000. A scalable approach to thread-level speculation . In 27th International Symposium on Computer Architecture. 10 .1145\/339647.339650 Steffan, J. G., Colohan, C. B., Zhai, A., and Mowry, T. C. 2000. A scalable approach to thread-level speculation. In 27th International Symposium on Computer Architecture. 10.1145\/339647.339650"},{"key":"e_1_2_1_38_1","volume-title":"7th International Symposium on High-Performance Computer Architecture.","author":"Tune E.","unstructured":"Tune , E. , Liang , D. , Tullsen , D. M. , and Calder , B . 2001. Dynamic prediction of critical path instructions . In 7th International Symposium on High-Performance Computer Architecture. Tune, E., Liang, D., Tullsen, D. M., and Calder, B. 2001. Dynamic prediction of critical path instructions. In 7th International Symposium on High-Performance Computer Architecture."},{"key":"e_1_2_1_39_1","volume-title":"11th International Conference on Parallel Architectures and Compilation Techniques.","author":"Tune E.","unstructured":"Tune , E. , Tullsen , D. , and Calder , B . 2002. Quantifying instruction criticality . In 11th International Conference on Parallel Architectures and Compilation Techniques. Tune, E., Tullsen, D., and Calder, B. 2002. Quantifying instruction criticality. In 11th International Conference on Parallel Architectures and Compilation Techniques."},{"key":"e_1_2_1_40_1","volume-title":"9th International Symposium on High Performance Computer Architecture.","author":"Yi J. J.","unstructured":"Yi , J. J. , Lilja , D. J. , and Hawkins , D. M . 2003. A statistically rigorous approach for improving simulation methodology . In 9th International Symposium on High Performance Computer Architecture. Yi, J. J., Lilja, D. J., and Hawkins, D. M. 2003. A statistically rigorous approach for improving simulation methodology. In 9th International Symposium on High Performance Computer Architecture."},{"key":"e_1_2_1_41_1","volume-title":"Supercomputing '96","author":"Zagha M.","unstructured":"Zagha , M. , Larson , B. , Turner , S. , and Itzkowitz , M . 1996. Performance analysis using the MIPS R10000 performance counters . In Supercomputing '96 . 10.1145\/369028.369059 Zagha, M., Larson, B., Turner, S., and Itzkowitz, M. 1996. Performance analysis using the MIPS R10000 performance counters. In Supercomputing '96. 10.1145\/369028.369059"},{"key":"e_1_2_1_42_1","volume-title":"Proceedings of the 28th International Symposium on Computer Architecture. 10","author":"Zilles C.","unstructured":"Zilles , C. and Sohi , G . 2001. Execution-based prediction using speculative slices . In Proceedings of the 28th International Symposium on Computer Architecture. 10 .1145\/379240.379246 Zilles, C. and Sohi, G. 2001. Execution-based prediction using speculative slices. In Proceedings of the 28th International Symposium on Computer Architecture. 10.1145\/379240.379246"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1022969.1022971","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1022969.1022971","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:41:25Z","timestamp":1750282885000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1022969.1022971"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,9]]},"references-count":42,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2004,9]]}},"alternative-id":["10.1145\/1022969.1022971"],"URL":"https:\/\/doi.org\/10.1145\/1022969.1022971","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2004,9]]},"assertion":[{"value":"2004-09-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}