{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:44:23Z","timestamp":1750308263942,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,9,22]],"date-time":"2004-09-22T00:00:00Z","timestamp":1095811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,9,22]]},"DOI":"10.1145\/1023833.1023852","type":"proceedings-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T17:39:48Z","timestamp":1097170788000},"page":"124-131","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Static next sub-bank prediction for drowsy instruction cache"],"prefix":"10.1145","author":[{"given":"Bramha","family":"Allu","sequence":"first","affiliation":[{"name":"Southern Illinois University Carbondale, Carbondale, IL"}]},{"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"Southern Illinois University Carbondale, Carbondale, IL"}]}],"member":"320","published-online":{"date-parts":[[2004,9,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687996"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920821"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_3_2_1_4_1","volume-title":"Proc. of PACT","author":"Zhou H.","year":"2001","unstructured":"H. Zhou , M. C. Toburen , E. Rotenberg , and T. M. Conte . Adaptive mode control: a static power-efficient cache design . In Proc. of PACT , 2001 . H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive mode control: a static power-efficient cache design. In Proc. of PACT, 2001."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774885"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545232"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545231"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360148"},{"key":"e_1_3_2_1_9_1","unstructured":"http:\/\/www.trimaran.org.  http:\/\/www.trimaran.org."},{"key":"e_1_3_2_1_10_1","unstructured":"http:\/\/www.spec.org.  http:\/\/www.spec.org."},{"key":"e_1_3_2_1_11_1","first-page":"330","volume-title":"Proc. the International Symposium on Microarchitecture","author":"Lee C.","year":"1997","unstructured":"C. Lee and M. Potkonjak , and W. H. Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems . In Proc. the International Symposium on Microarchitecture , pp. 330 -- 335 , 1997 . C. Lee and M. Potkonjak, and W. H. Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In Proc. the International Symposium on Microarchitecture, pp. 330--335, 1997."},{"key":"e_1_3_2_1_12_1","volume-title":"Research Report","author":"Shivakumar P.","year":"2001","unstructured":"P. Shivakumar and N. Jouppi . CACTI 3.0: An integrated cache timing, power and area model. WRL Research Report 2001 . P. Shivakumar and N. Jouppi. CACTI 3.0: An integrated cache timing, power and area model. WRL Research Report 2001."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774884"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155119"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74951"}],"event":{"name":"CASES04: 2004 International Conference on Compilers, Architectures and Synthesis for Embedded Systems","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Washington DC USA","acronym":"CASES04"},"container-title":["Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1023833.1023852","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1023833.1023852","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T17:23:53Z","timestamp":1750267433000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1023833.1023852"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,9,22]]},"references-count":15,"alternative-id":["10.1145\/1023833.1023852","10.1145\/1023833"],"URL":"https:\/\/doi.org\/10.1145\/1023833.1023852","relation":{},"subject":[],"published":{"date-parts":[[2004,9,22]]},"assertion":[{"value":"2004-09-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}