{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:44:24Z","timestamp":1750308264329,"version":"3.41.0"},"reference-count":15,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2003,9,27]],"date-time":"2003-09-27T00:00:00Z","timestamp":1064620800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2004,6]]},"abstract":"<jats:p>\n            The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-Bit AMBA AHB bus. Its memory subsystem is particularly adapted to the high bandwidth demands of the multi-core architecture by providing several DMA capabilities and multiple data transfer paths. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 \u03bcm 6LM standard-cell technology, occupies about 82 mm\n            <jats:sup>2<\/jats:sup>\n            , operates at 145 MHz, and comsumes 3.5 Watts.\n          <\/jats:p>","DOI":"10.1145\/1024295.1024303","type":"journal-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T17:39:09Z","timestamp":1097170749000},"page":"55-61","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["HIBRID-SOC"],"prefix":"10.1145","volume":"32","author":[{"given":"S.","family":"Moch","sequence":"first","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]},{"given":"M.","family":"Berekovi\u0107","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]},{"given":"H. J.","family":"Stolberg","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]},{"given":"L.","family":"Friebe","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]},{"given":"M. B.","family":"Kulaczewski","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]},{"given":"A.","family":"Dehnhardt","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]},{"given":"P.","family":"Pirsch","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Hannover, Germany"}]}],"member":"320","published-online":{"date-parts":[[2003,9,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ISO\/IEC JTC1\/SC29\/WG11 N4668 \"Overview of the MPEG-4 Standard \" Jeju March 2002.  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Pirsch, and Holger Runge, \"The MPEG-4 Advanced Simple Profile - A Complexity Study,\" Proc. of 2nd Workshop and Exhibition on MPEG-4, pp. 33--36, June 2001."},{"key":"e_1_2_1_12_1","volume-title":"Synthetic aperture radar: Systems and signal processing","author":"Curlander J.","year":"1991","unstructured":"J. Curlander , R. McDonough , Synthetic aperture radar: Systems and signal processing , Wiley-Interscience , 1991 . J. Curlander, R. McDonough, Synthetic aperture radar: Systems and signal processing, Wiley-Interscience, 1991."},{"key":"e_1_2_1_13_1","volume-title":"A New DSP for Onboard Real-Time SAR Systems,\" Proceedings of the 15th Aerosense Conference on Photonic and Quantum Technologies for Aerospace Applications III","author":"Kloos H.","year":"2001","unstructured":"H. Kloos , L. Friebe , J. P. Wittenburg , W. Hinrichs , H. Lieske , and P. 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