{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:45:53Z","timestamp":1772163953654,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":112,"publisher":"ACM","license":[{"start":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T00:00:00Z","timestamp":1097107200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2004,10,7]]},"DOI":"10.1145\/1024393.1024396","type":"proceedings-article","created":{"date-parts":[[2004,10,7]],"date-time":"2004-10-07T13:39:48Z","timestamp":1097156388000},"page":"14-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":58,"title":["Spatial computation"],"prefix":"10.1145","author":[{"given":"Mihai","family":"Budiu","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}]},{"given":"Girish","family":"Venkataramani","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}]},{"given":"Tiberiu","family":"Chelcea","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}]},{"given":"Seth Copen","family":"Goldstein","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}]}],"member":"320","published-online":{"date-parts":[[2004,10,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"http:\/\/public.itrs.net\/Files\/1999 SIA Roadmap\/Design.pdf","author":"International","year":"1999","unstructured":"International technology roadmap for semiconductors (ITRS). http:\/\/public.itrs.net\/Files\/1999 SIA Roadmap\/Design.pdf , 1999 .]] International technology roadmap for semiconductors (ITRS). http:\/\/public.itrs.net\/Files\/1999 SIA Roadmap\/Design.pdf, 1999.]]"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339691"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/212094.212131"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.823443"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/278283.278285"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307528"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/800046.801684"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266810"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/795658.795878"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.726547"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(91)90016-3"},{"key":"e_1_3_2_1_12_1","first-page":"152","volume-title":"Workshops in Computing","author":"van Berkel Kees","year":"1995","unstructured":"Kees van Berkel and Martin Rem . VLSI programming of asynchronous circuits for low power. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design , Workshops in Computing , pages 152 -- 210 . Springer Verlag , 1995 . summary at www.cse.ttu.edu.tw\/ cheng\/courses\/soc\/S02\/AsyncSoc08.ppt; also Nat.Lab. Technical Note Nr. UR 005\/94, Philips Research Laboratories, Eindhoven, the Netherlands.]] Kees van Berkel and Martin Rem. VLSI programming of asynchronous circuits for low power. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 152--210. Springer Verlag, 1995. summary at www.cse.ttu.edu.tw\/ cheng\/courses\/soc\/S02\/AsyncSoc08.ppt; also Nat.Lab. Technical Note Nr. UR 005\/94, Philips Research Laboratories, Eindhoven, the Netherlands.]]"},{"key":"e_1_3_2_1_13_1","volume-title":"Logic Minimization Algorithms for Digital Circuits","author":"Brayton R.","year":"1984","unstructured":"R. Brayton , A. Sangiovanni-Vincentelli , G. Hachtel , and C. McMullin . Logic Minimization Algorithms for Digital Circuits . Kluwer Academic Publishers , Boston, MA , 1984 .]] R. Brayton, A. Sangiovanni-Vincentelli, G. Hachtel, and C. McMullin. Logic Minimization Algorithms for Digital Circuits. Kluwer Academic Publishers, Boston, MA, 1984.]]"},{"key":"e_1_3_2_1_14_1","first-page":"302","volume-title":"International Workshop on Logic Synthesis","author":"Brej C.F.","year":"2003","unstructured":"C.F. Brej and J.D. Garside . Early output logic using anti-tokens . In International Workshop on Logic Synthesis , pages 302 -- 309 , May 2003 .]] C.F. Brej and J.D. Garside. Early output logic using anti-tokens. In International Workshop on Logic Synthesis, pages 302--309, May 2003.]]"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/647929.740544"},{"key":"e_1_3_2_1_18_1","first-page":"216","volume-title":"International ACM\/IEEE Symposium on Code Generation and Optimization (CGO)","author":"Budiu Mihai","year":"2003","unstructured":"Mihai Budiu and Seth Copen Goldstein . Optimizing memory accesses for spatial computation . In International ACM\/IEEE Symposium on Code Generation and Optimization (CGO) , pages 216 -- 227 , San Francisco, CA , March 23-26 2003 .]] Mihai Budiu and Seth Copen Goldstein. Optimizing memory accesses for spatial computation. In International ACM\/IEEE Symposium on Code Generation and Optimization (CGO), pages 216--227, San Francisco, CA, March 23-26 2003.]]"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/795660.795951"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"e_1_3_2_1_22_1","series-title":"Lecture Notes in Computer Science","volume-title":"International Conference on Field Programmable Logic and Applications (FPL)","author":"Timothy","year":"1998","unstructured":"Timothy J. Callahan and John Wawrzynek. Instruction level parallelism for reconfigurable computing . In Hartenstein and Keevallik, editors, International Conference on Field Programmable Logic and Applications (FPL) , volume 1482 of Lecture Notes in Computer Science , Tallinin, Estonia, September 1998 . Springer-Verlag .]] Timothy J. Callahan and John Wawrzynek. Instruction level parallelism for reconfigurable computing. In Hartenstein and Keevallik, editors, International Conference on Field Programmable Logic and Applications (FPL), volume 1482 of Lecture Notes in Computer Science, Tallinin, Estonia, September 1998. Springer-Verlag.]]"},{"key":"e_1_3_2_1_23_1","volume-title":"International Conference on Field Programmable Logic and Applications (FPL), Montpellier (La Grande-Motte)","author":"Joao M.","year":"2002","unstructured":"Joao M. P. Cardoso and Markus Weinhardt. PXPP-VC: A C compiler with temporal partitioning for the PACT-XPP architecture . In International Conference on Field Programmable Logic and Applications (FPL), Montpellier (La Grande-Motte) , France , September 2002 .]] Joao M. P. Cardoso and Markus Weinhardt. PXPP-VC: A C compiler with temporal partitioning for the PACT-XPP architecture. In International Conference on Field Programmable Logic and Applications (FPL), Montpellier (La Grande-Motte), France, September 2002.]]"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/520793.825741"},{"key":"e_1_3_2_1_25_1","volume-title":"International Journal of Parallel Programming, special issue, 28(6)","author":"Carter Lori","year":"2000","unstructured":"Lori Carter , Beth Simon , Brad Calder , Larry Carter , and Jeanne Ferrante . Path analysis and renaming for predicated instruction scheduling . International Journal of Parallel Programming, special issue, 28(6) , 2000 .]] Lori Carter, Beth Simon, Brad Calder, Larry Carter, and Jeanne Ferrante. Path analysis and renaming for predicated instruction scheduling. International Journal of Parallel Programming, special issue, 28(6), 2000.]]"},{"key":"e_1_3_2_1_26_1","series-title":"Lecture Notes in Computer Science","volume-title":"International Conference on Field Programmable Logic and Applications (FPL)","author":"Caspi Eylon","year":"2000","unstructured":"Eylon Caspi , Michael Chu , Randy Huang , Joseph Yeh , Yury Markovskiy , Andre DeHon , and John Wawrzynek . Stream computations organized for reconfigurable execution (SCORE): Introduction and tutorial . In International Conference on Field Programmable Logic and Applications (FPL) , Lecture Notes in Computer Science . Springer Verlag , 2000 .]] Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy, Andre DeHon, and John Wawrzynek. Stream computations organized for reconfigurable execution (SCORE): Introduction and tutorial. In International Conference on Field Programmable Logic and Applications (FPL), Lecture Notes in Computer Science. Springer Verlag, 2000.]]"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514023"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/647473.760381"},{"key":"e_1_3_2_1_29_1","first-page":"22","volume-title":"IEEE International Solid-State Circuits Conference","author":"Claasen T.A.C.M.","year":"1999","unstructured":"T.A.C.M. Claasen . High speed: not the only way to exploit the intrinsic computational power of silicon . In IEEE International Solid-State Circuits Conference , pages 22 -- 25 , San Francisco, CA , 1999 . IEEE Catalog Number: 99CH36278.]] T.A.C.M. Claasen. High speed: not the only way to exploit the intrinsic computational power of silicon. In IEEE International Solid-State Circuits Conference, pages 22--25, San Francisco, CA, 1999. IEEE Catalog Number: 99CH36278.]]"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/773146.773049"},{"key":"e_1_3_2_1_31_1","volume-title":"Handel-C language reference manual","author":"Celoxica Corporation","year":"2003","unstructured":"Celoxica Corporation . Handel-C language reference manual , 2003 .]] Celoxica Corporation. Handel-C language reference manual, 2003.]]"},{"key":"e_1_3_2_1_32_1","unstructured":"CoWare Inc. Flexible platform-based design with the CoWare N2C design system October 2000.]]  CoWare Inc. Flexible platform-based design with the CoWare N2C design system October 2000.]]"},{"key":"e_1_3_2_1_33_1","first-page":"141","volume-title":"International Symposium on Computer Architecture (ISCA)","author":"David","year":"1988","unstructured":"David E. Culler and Arvind. Resource requirements of dataflow programs . In International Symposium on Computer Architecture (ISCA) , pages 141 -- 150 , 1988 .]] David E. Culler and Arvind. Resource requirements of dataflow programs. In International Symposium on Computer Architecture (ISCA), pages 141--150, 1988.]]"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155094"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337604"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.987095"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/647243.760157"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.5555\/647323.721501"},{"key":"e_1_3_2_1_40_1","volume-title":"Workshop on Languages and Compilers for Parallel Computing (LCPC)","author":"Diniz Pedro","year":"2001","unstructured":"Pedro Diniz , Mary Hall , Joonseok Park , Byoungro So , and Heidi Ziegler . Bridging the gap between compilation and synthesis in the DEFACTO system . In Workshop on Languages and Compilers for Parallel Computing (LCPC) , 2001 .]] Pedro Diniz, Mary Hall, Joonseok Park, Byoungro So, and Heidi Ziegler. Bridging the gap between compilation and synthesis in the DEFACTO system. In Workshop on Languages and Compilers for Parallel Computing (LCPC), 2001.]]"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795752"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/45.1.12"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545222"},{"key":"e_1_3_2_1_45_1","volume-title":"An open graph visualization system and its applications to software engineering. Software Practice And Experience, 1(5)","author":"Gansner Emden","year":"1999","unstructured":"Emden Gansner and Stephen North . An open graph visualization system and its applications to software engineering. Software Practice And Experience, 1(5) , 1999 . http:\/\/www.research.att.com\/sw\/tools\/graphviz.]] Emden Gansner and Stephen North. An open graph visualization system and its applications to software engineering. Software Practice And Experience, 1(5), 1999. http:\/\/www.research.att.com\/sw\/tools\/graphviz.]]"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313920"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307529"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/647922.741012"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795916"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379262"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300982"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.604077"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514140"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378481"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_57_1","volume-title":"Essays in Computing Science","year":"1989","unstructured":"Hoare. Communicating sequential processes . In C. A. A. Hoare and C. B. Jones (Ed.), Essays in Computing Science , Prentice Hall . 1989 .]] Hoare. Communicating sequential processes. In C. A. A. Hoare and C. B. Jones (Ed.), Essays in Computing Science, Prentice Hall. 1989.]]"},{"key":"e_1_3_2_1_58_1","volume-title":"IEEE\/ACM International Conference on Computer-aided design (ICCAD)","author":"James","year":"2000","unstructured":"James C. Hoe and Arvind. Synthesis of operation-centric hardware descriptions . In IEEE\/ACM International Conference on Computer-aided design (ICCAD) , San Jose, California , November 2000 .]] James C. Hoe and Arvind. Synthesis of operation-centric hardware descriptions. In IEEE\/ACM International Conference on Computer-aided design (ICCAD), San Jose, California, November 2000.]]"},{"key":"e_1_3_2_1_59_1","first-page":"34","article-title":"Programming a Xilinx FPGA in \"C","author":"Johnson Doug","year":"1999","unstructured":"Doug Johnson . Programming a Xilinx FPGA in \"C \". Xcell Quarterly Journal , 34 , 1999 .]] Doug Johnson. Programming a Xilinx FPGA in \"C\". Xcell Quarterly Journal, 34, 1999.]]","journal-title":"Xcell Quarterly Journal"},{"key":"e_1_3_2_1_60_1","volume-title":"IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Kay Andrew","year":"1999","unstructured":"Andrew Kay , Toshio Nomura , Akihisa Yamada , Koichi Nishida , Ryoji Sakurai , and Takashi Kambe . Hardware synthesis with Bach system . In IEEE International Symposium on Circuits and Systems (ISCAS) , Orlando , 1999 .]] Andrew Kay, Toshio Nomura, Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, and Takashi Kambe. Hardware synthesis with Bach system. In IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, 1999.]]"},{"key":"e_1_3_2_1_61_1","series-title":"Software Series","volume-title":"The C Programming Language","author":"Kernighan Brian W.","year":"1988","unstructured":"Brian W. Kernighan and Dennis M. Ritchie . The C Programming Language . Software Series . Prentice Hall , 2 edition, 1988 .]] Brian W. Kernighan and Dennis M. Ritchie. The C Programming Language. Software Series. Prentice Hall, 2 edition, 1988.]]"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.139702"},{"key":"e_1_3_2_1_64_1","volume-title":"the 1998 International Conference on Compiler Construction","volume":"1383","author":"Lapkowski Christopher","year":"1998","unstructured":"Christopher Lapkowski and Laurie J. Hendren . Extended SSA numbering: Introducing SSA properties to languages with multi-level pointers . In the 1998 International Conference on Compiler Construction , volume 1383 of Lecture Notes in Computer Science, pages 128- -143, March 1998 .]] Christopher Lapkowski and Laurie J. Hendren. Extended SSA numbering: Introducing SSA properties to languages with multi-level pointers. In the 1998 International Conference on Compiler Construction, volume 1383 of Lecture Notes in Computer Science, pages 128--143, March 1998.]]"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309989"},{"key":"e_1_3_2_1_66_1","first-page":"330","volume-title":"IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Lee Chunho","year":"1997","unstructured":"Chunho Lee , Miodrag Potkonjak , and William H . Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems . In IEEE\/ACM International Symposium on Microarchitecture (MICRO) , pages 330 -- 335 , 1997 .]] Chunho Lee, Miodrag Potkonjak, and William H. Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In IEEE\/ACM International Symposium on Microarchitecture (MICRO), pages 330--335, 1997.]]"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291018"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337559"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266037"},{"key":"e_1_3_2_1_70_1","volume-title":"Pipelined asynchronous circuits. Master's thesis","author":"Lines Andrew Matthew","year":"1995","unstructured":"Andrew Matthew Lines . Pipelined asynchronous circuits. Master's thesis , California Institute of Technology, Computer Science Department , 1995 . CS-TR-95-21.]] Andrew Matthew Lines. Pipelined asynchronous circuits. Master's thesis, California Institute of Technology, Computer Science Department, 1995. CS-TR-95-21.]]"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277659"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/258915.258943"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.225965"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.144998"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339673"},{"key":"e_1_3_2_1_76_1","series-title":"UT Year of Programming Series","first-page":"1","volume-title":"Developments in Concurrency and Communication","author":"Martin A. J.","year":"1990","unstructured":"A. J. Martin . Programming in VLSI: From communicating processes to delay-insensitive circuits . In C. A. R. Hoare, editor, Developments in Concurrency and Communication , UT Year of Programming Series , pages 1 -- 64 . Addison-Wesley , 1990 .]] A. J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C. A. R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series, pages 1--64. Addison-Wesley, 1990.]]"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.5555\/785169.785385"},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795903"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1145\/948176.948183"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307527"},{"key":"e_1_3_2_1_81_1","first-page":"204","volume-title":"International Symposium on the Theory of Switching Functions","author":"Muller David E.","year":"1959","unstructured":"David E. Muller and W. S. Bartky . A theory of asynchronous circuits . In International Symposium on the Theory of Switching Functions , pages 204 -- 243 , 1959 .]] David E. Muller and W. S. Bartky. A theory of asynchronous circuits. In International Symposium on the Theory of Switching Functions, pages 204--243, 1959.]]"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/93542.93578"},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1145\/99583.99595"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192749"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.954998"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920828"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.5555\/290940.290946"},{"key":"e_1_3_2_1_88_1","volume-title":"IEEE International High Level Design Validation and Test Workshop","author":"Roth Ray","year":"1999","unstructured":"Ray Roth and Dinesh Ramanathan . A high-level design methodology using C++ . In IEEE International High Level Design Validation and Test Workshop , November 1999 .]] Ray Roth and Dinesh Ramanathan. A high-level design methodology using C++. In IEEE International High Level Design Validation and Test Workshop, November 1999.]]"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3337-2_7"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277135"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/224164.224208"},{"key":"e_1_3_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.642817"},{"key":"e_1_3_2_1_93_1","volume-title":"Journal of VLSI Signal Processing","author":"Schreiber R.","year":"2001","unstructured":"R. Schreiber , S. Aditya (Gupta), B.R. Rau , S. Mahlke , V. Kathail , B. Ra. Rau , D. Cronquist , and M. Sivaraman . PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators . Journal of VLSI Signal Processing , 2001 .]] R. Schreiber, S. Aditya (Gupta), B.R. Rau, S. Mahlke, V. Kathail, B. Ra. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 2001.]]"},{"key":"e_1_3_2_1_94_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.974889"},{"key":"e_1_3_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360322"},{"key":"e_1_3_2_1_96_1","first-page":"339","volume-title":"IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Soderman Donald","year":"1998","unstructured":"Donald Soderman and Yuri Panchul . Implementing C algorithms in reconfigurable hardware using C2Verilog. In Kenneth L. Pocek and Jeffrey Arnold, editors , IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , pages 339 -- 342 , Los Alamitos, CA , April 1998 . IEEE Computer Society Press.]] Donald Soderman and Yuri Panchul. Implementing C algorithms in reconfigurable hardware using C2Verilog. In Kenneth L. Pocek and Jeffrey Arnold, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 339--342, Los Alamitos, CA, April 1998. IEEE Computer Society Press.]]"},{"key":"e_1_3_2_1_97_1","doi-asserted-by":"publisher","DOI":"10.1145\/202529.202536"},{"key":"e_1_3_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"e_1_3_2_1_99_1","volume-title":"Technical Report 2003-01-01","author":"Swanson Steven","year":"2003","unstructured":"Steven Swanson , Ken Michelson , and Mark Oskin . WaveScalar. Technical Report 2003-01-01 , Washington University at Seattle, Computer Science Department , January 2003 .]] Steven Swanson, Ken Michelson, and Mark Oskin. WaveScalar. Technical Report 2003-01-01, Washington University at Seattle, Computer Science Department, January 2003.]]"},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.5555\/846225.848233"},{"key":"e_1_3_2_1_101_1","first-page":"17","volume-title":"International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC)","author":"Teifel John","year":"2004","unstructured":"John Teifel and Rajit Manohar . Static tokens : Using dataflow to automate oncurrent pipeline synthesis . In International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) , pages 17 -- 27 , Heraklion, Crete, Greece , April 2004 .]] John Teifel and Rajit Manohar. Static tokens: Using dataflow to automate oncurrent pipeline synthesis. In International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 17--27, Heraklion, Crete, Greece, April 2004.]]"},{"key":"e_1_3_2_1_102_1","unstructured":"Herve Touati and Mark Shand. PamDC: a C++ library for the simulation and generation of Xilinx FPGA designs. http:\/\/research.compaq.com\/SRC\/pamette\/PamDC.pdf 1999.]]  Herve Touati and Mark Shand. PamDC: a C++ library for the simulation and generation of Xilinx FPGA designs. http:\/\/research.compaq.com\/SRC\/pamette\/PamDC.pdf 1999.]]"},{"key":"e_1_3_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775880"},{"key":"e_1_3_2_1_104_1","series-title":"Intl","volume-title":"Handshake Circuits: An Asynchronous Architecture for VLSI Programming","author":"van Berkel Kees","year":"1993","unstructured":"Kees van Berkel . Handshake Circuits: An Asynchronous Architecture for VLSI Programming , volume 5 of Intl . Series on Parallel Computation. Cambridge University Press , 1993 .]] Kees van Berkel. Handshake Circuits: An Asynchronous Architecture for VLSI Programming, volume 5 of Intl. Series on Parallel Computation. Cambridge University Press, 1993.]]"},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(90)90033-L"},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1145\/27633.28055"},{"key":"e_1_3_2_1_107_1","volume-title":"International Workshop on Logic Syntheiss","author":"Venkataramani Girish","year":"2004","unstructured":"Girish Venkataramani , Mihai Budiu , and Seth Copen Goldstein . C to asynchronous dataflow circuits: An end-to-end toolflow . In International Workshop on Logic Syntheiss , Temecula, CA , June 2004 .]] Girish Venkataramani, Mihai Budiu, and Seth Copen Goldstein. C to asynchronous dataflow circuits: An end-to-end toolflow. In International Workshop on Logic Syntheiss, Temecula, CA, June 2004.]]"},{"key":"e_1_3_2_1_108_1","volume-title":"Moore School of Electrical Engineering","author":"von Neumann John","year":"1982","unstructured":"John von Neumann . First draft of a report on the EDVAC. Contract No. W-670-ORD-492 , Moore School of Electrical Engineering , University of Pennsylvania, Philadelphia. Reprinted (in part) in Randell, Brian. 1982 . Origins of Digital Computers: Selected Papers, Springer-Verlag , Berlin Heidelberg, June 1945.]] John von Neumann. First draft of a report on the EDVAC. Contract No. W-670-ORD-492, Moore School of Electrical Engineering, University of Pennsylvania, Philadelphia. Reprinted (in part) in Randell, Brian. 1982. Origins of Digital Computers: Selected Papers, Springer-Verlag, Berlin Heidelberg, June 1945.]]"},{"key":"e_1_3_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.898829"},{"key":"e_1_3_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279484"},{"key":"e_1_3_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/193209.193217"},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.683004"},{"key":"e_1_3_2_1_113_1","first-page":"99","volume-title":"IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Wirthlin M. J.","year":"1995","unstructured":"M. J. Wirthlin and B. L. Hutchings . A dynamic instruction set computer. In P. Athanas and K. L. Pocek, editors , IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , pages 99 -- 107 , Napa, CA , April 1995 .]] M. J. Wirthlin and B. L. Hutchings. A dynamic instruction set computer. In P. Athanas and K. L. Pocek, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 99--107, Napa, CA, April 1995.]]"},{"key":"e_1_3_2_1_114_1","first-page":"126","volume-title":"IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Wittig R. D.","year":"1996","unstructured":"R. D. Wittig and P. Chow . OneChip: An FPGA processor with reconfigurable logic. In J. Arnold and K. L. Pocek, editors , IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , pages 126 -- 135 , Napa, CA , April 1996 .]] R. D. Wittig and P. Chow. OneChip: An FPGA processor with reconfigurable logic. In J. Arnold and K. L. Pocek, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 126--135, Napa, CA, April 1996.]]"},{"key":"e_1_3_2_1_115_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339687"},{"key":"e_1_3_2_1_116_1","unstructured":"Ning Zhang and Bob Brodersen. The cost of flexibility in systems on a chip design for signal processing applications. http:\/\/bwrc.eecs.berkeley.edu\/Classes\/EE225C\/Papers\/arch design.doc Spring 2002.]]  Ning Zhang and Bob Brodersen. The cost of flexibility in systems on a chip design for signal processing applications. http:\/\/bwrc.eecs.berkeley.edu\/Classes\/EE225C\/Papers\/arch design.doc Spring 2002.]]"}],"event":{"name":"ASPLOS04: Architectural Support for Programming Languages and Operating Systems","location":"Boston MA USA","acronym":"ASPLOS04","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 11th international conference on Architectural support for programming languages and operating systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1024393.1024396","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1024393.1024396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:23:54Z","timestamp":1750253034000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1024393.1024396"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,10,7]]},"references-count":112,"alternative-id":["10.1145\/1024393.1024396","10.1145\/1024393"],"URL":"https:\/\/doi.org\/10.1145\/1024393.1024396","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1037187.1024396","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1037949.1024396","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1037947.1024396","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2004,10,7]]},"assertion":[{"value":"2004-10-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}