{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:44Z","timestamp":1772724824246,"version":"3.50.1"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2004,12,1]],"date-time":"2004-12-01T00:00:00Z","timestamp":1101859200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2004,12]]},"abstract":"<jats:p>\n            The continuously increasing gap between processor and memory speeds is a serious limitation to the performance achievable by future microprocessors. Currently, processors tolerate long-latency memory operations largely by maintaining a high number of in-flight instructions. In the future, this may require supporting many hundreds, or even thousands, of in-flight instructions. Unfortunately, the traditional approach of scaling up critical processor structures to provide such support is impractical at these levels, due to area, power, and cycle time constraints.In this paper we show that, in order to overcome this resource-scalability problem, the way in which critical processor resources are managed must be changed. Instead of simply upsizing the processor structures, we propose a smarter use of the available resources, supported by a selective checkpointing mechanism. This mechanism allows instructions to commit out of order, and makes a reorder buffer unnecessary. We present a set of techniques such as multilevel instruction queues, late allocation and early release of registers, and early release of load\/store queue entries. All together, these techniques constitute what we call a\n            <jats:italic>kilo-instruction processor<\/jats:italic>\n            , an architecture that can support thousands of in-flight instructions, and thus may achieve high performance even in the presence of large memory access latencies.\n          <\/jats:p>","DOI":"10.1145\/1044823.1044825","type":"journal-article","created":{"date-parts":[[2005,8,1]],"date-time":"2005-08-01T17:31:42Z","timestamp":1122917502000},"page":"389-417","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":57,"title":["Toward kilo-instruction processors"],"prefix":"10.1145","volume":"1","author":[{"given":"Adri\u00e1n","family":"Cristal","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliverio J.","family":"Santana","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 F.","family":"Mart\u00ednez","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,12]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the 36th International Symposium on Microarchitecture","author":"Akkary H.","unstructured":"Akkary , H. , Rajwar , R. , and Srinivasan , S. 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In Proceedings of Supercomputing'91 (Albuquerque, NM). 176--186. 10.1145\/125826.125932"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the 35th International Symposium on Microarchitecture","author":"Brekelbaum E.","unstructured":"Brekelbaum , E. , Rupley , J. , Wilkerson , C. , and Black , B . 2002. Hierarchical scheduling windows . In Proceedings of the 35th International Symposium on Microarchitecture ( Istanbul, Turkey). 27--36. Brekelbaum, E., Rupley, J., Wilkerson, C., and Black, B. 2002. Hierarchical scheduling windows. In Proceedings of the 35th International Symposium on Microarchitecture (Istanbul, Turkey). 27--36."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/362686.362692"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the 31st International Symposium on Computer Architecture","author":"Cain H. W.","unstructured":"Cain , H. W. and Lipasti , M. H . 2004. Memory ordering: A value-based approach . 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Also submitted to the 35th International Symposium on Microarchitecture in 2002.  Cristal A. Valero M. Gonzalez A. and Llosa J. 2002b. Large Virtual ROBs by Processor Checkpointing. Technical Report UPC-DAC-2002-39 Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona Spain. Also submitted to the 35th International Symposium on Microarchitecture in 2002."},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Cristal A. Mart\u00ednez J. F. Llosa J. and Valero M. 2003a. A case for resource-conscious out-of-order processors. IEEE TCCA Computer Architecture Letters 2. 10.1109\/L-CA.2003.4   Cristal A. Mart\u00ednez J. F. Llosa J. and Valero M. 2003a. A case for resource-conscious out-of-order processors. IEEE TCCA Computer Architecture Letters 2. 10.1109\/L-CA.2003.4","DOI":"10.1145\/1152923.1024296"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the 5th International Symposium on High-Performance Computing","author":"Cristal A.","unstructured":"Cristal , A. , Ortega , D. , Llosa , J. , and Valero , M . 2003b. Kilo-instruction processors . In Proceedings of the 5th International Symposium on High-Performance Computing ( Tokyo, Japan). 10--25. Keynote paper. Cristal, A., Ortega, D., Llosa, J., and Valero, M. 2003b. Kilo-instruction processors. In Proceedings of the 5th International Symposium on High-Performance Computing (Tokyo, Japan). 10--25. Keynote paper."},{"key":"e_1_2_1_14_1","volume-title":"Technical Report UPC-DAC-2003-51, Departament d'Arquitectura de Computadors, Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain.","author":"Cristal A.","year":"2003","unstructured":"Cristal , A. , Mart\u00ednez , J. F. , Llosa , J. , and Valero , M . 2003 c. Ephemeral Registers with Multicheckpointing . Technical Report UPC-DAC-2003-51, Departament d'Arquitectura de Computadors, Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain. Cristal, A., Mart\u00ednez, J. F., Llosa, J., and Valero, M. 2003c. Ephemeral Registers with Multicheckpointing. Technical Report UPC-DAC-2003-51, Departament d'Arquitectura de Computadors, Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10008"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the Euro-Par Conference","author":"Cristal A.","unstructured":"Cristal , A. , Santana , O. J. , and Valero , M . 2004b. Maintaining thousands of in-flight instructions . In Proceedings of the Euro-Par Conference ( Pisa, Italy). Keynote paper. Cristal, A., Santana, O. J., and Valero, M. 2004b. Maintaining thousands of in-flight instructions. In Proceedings of the Euro-Par Conference (Pisa, Italy). Keynote paper."},{"key":"e_1_2_1_17_1","unstructured":"Dubois M. and Song Y. 1998. Assisted Execution. Technical Report CENG 98--25 Department of EE-Systems University of Southern California Los Angeles CA.  Dubois M. and Song Y. 1998. Assisted Execution. Technical Report CENG 98--25 Department of EE-Systems University of Southern California Los Angeles CA."},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the 9th International Conference on Supercomputing","author":"Dundas J.","unstructured":"Dundas , J. and Mudge , T . 1997. Improving data cache performance by pre-executing instructions under a cache miss . In Proceedings of the 9th International Conference on Supercomputing ( Vienna, Austria). 68--75. 10.1145\/263580.263597 Dundas, J. and Mudge, T. 1997. Improving data cache performance by pre-executing instructions under a cache miss. In Proceedings of the 9th International Conference on Supercomputing (Vienna, Austria). 68--75. 10.1145\/263580.263597"},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the 1st Conference on Computer Frontiers","author":"Galluzzi M.","unstructured":"Galluzzi , M. , Puente , V. , Cristal , A. , Beivide , R. , Gregorio , J. A. , and Valero , M . 2004. A first glance at kilo-instruction based multiprocessors . In Proceedings of the 1st Conference on Computer Frontiers ( Ischia, Italy). 10.1145\/977091.977120 Galluzzi, M., Puente, V., Cristal, A., Beivide, R., Gregorio, J. A., and Valero, M. 2004. A first glance at kilo-instruction based multiprocessors. In Proceedings of the 1st Conference on Computer Frontiers (Ischia, Italy). 10.1145\/977091.977120"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the 14th International Symposium on Computer Architecture","author":"Hwu W. M.","unstructured":"Hwu , W. M. and Patt , Y. N . 1987. Checkpoint repair for out-of-order execution machines . In Proceedings of the 14th International Symposium on Computer Architecture ( Pittsburgh, PA). 18--26. 10.1145\/30350.30353 Hwu, W. M. and Patt, Y. N. 1987. Checkpoint repair for out-of-order execution machines. In Proceedings of the 14th International Symposium on Computer Architecture (Pittsburgh, PA). 18--26. 10.1145\/30350.30353"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the 24th International Symposium on Computer Architecture","author":"Joseph D.","unstructured":"Joseph , D. and Grunwald , D . 1997. Prefetching using Markov predictors . In Proceedings of the 24th International Symposium on Computer Architecture ( Denver, CO). 252--263. 10.1145\/264107.264207 Joseph, D. and Grunwald, D. 1997. Prefetching using Markov predictors. In Proceedings of the 24th International Symposium on Computer Architecture (Denver, CO). 252--263. 10.1145\/264107.264207"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 18th International Symposium on Computer Architecture","author":"Klaiber A.","unstructured":"Klaiber , A. and Levi , H . 1991. An architecture for software-controlled data prefetching . In Proceedings of the 18th International Symposium on Computer Architecture ( Toronto, Canada). 53--53. 10.1145\/115952.115958 Klaiber, A. and Levi, H. 1991. An architecture for software-controlled data prefetching. In Proceedings of the 18th International Symposium on Computer Architecture (Toronto, Canada). 53--53. 10.1145\/115952.115958"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the 29th International Symposium on Computer Architecture","author":"Lebeck A.","unstructured":"Lebeck , A. , Koppanalil , T. , Li , T. , Patwardhan , J. , and Rotenberg , E . 2002. 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In Proceedings of the 11st International Conference on Architectural Support for Programming Languages and Operating Systems (Boston, MA). 107--119. 10.1145\/1024393.1024407"},{"key":"e_1_2_1_40_1","doi-asserted-by":"crossref","unstructured":"Tendler J. M. Dodson S. Fields S. Le H. and Sinharoy B. 2001. IBM &commat;server POWER4 System Microarchitecture. IBM Technical White Paper. IBM Server Group.  Tendler J. M. Dodson S. Fields S. Le H. and Sinharoy B. 2001. IBM &commat;server POWER4 System Microarchitecture. IBM Technical White Paper. IBM Server Group.","DOI":"10.1147\/rd.461.0005"},{"key":"e_1_2_1_41_1","volume-title":"Proceedings of the 28th International Symposium on Computer Architecture","author":"Zilles C.","unstructured":"Zilles , C. and Sohi , G. S . 2001. Execution-based prediction using speculative slices . In Proceedings of the 28th International Symposium on Computer Architecture ( G\u00f6teborg, Sweden). 2--13. 10.1145\/379240.379246 Zilles, C. and Sohi, G. S. 2001. Execution-based prediction using speculative slices. In Proceedings of the 28th International Symposium on Computer Architecture (G\u00f6teborg, Sweden). 2--13. 10.1145\/379240.379246"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1044823.1044825","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1044823.1044825","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:36:48Z","timestamp":1750282608000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1044823.1044825"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,12]]},"references-count":41,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2004,12]]}},"alternative-id":["10.1145\/1044823.1044825"],"URL":"https:\/\/doi.org\/10.1145\/1044823.1044825","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2004,12]]},"assertion":[{"value":"2004-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}