{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:58:07Z","timestamp":1750309087387,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,2,20]],"date-time":"2005-02-20T00:00:00Z","timestamp":1108857600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,2,20]]},"DOI":"10.1145\/1046192.1046220","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:31:47Z","timestamp":1123057907000},"page":"215-226","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":36,"title":["Design, layout and verification of an FPGA using automated tools"],"prefix":"10.1145","author":[{"given":"Ian","family":"Kuon","sequence":"first","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}]},{"given":"Aaron","family":"Egier","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}]},{"given":"Jonathan","family":"Rose","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}]}],"member":"320","published-online":{"date-parts":[[2005,2,20]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.1145\/329166.329171"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1145\/329166.329203"},{"unstructured":"V. Betz and J. Rose. Automatic generation of programmable logic device architectures October 2003. US Patent 6 631 510. V. Betz and J. Rose. Automatic generation of programmable logic device architectures October 2003. US Patent 6 631 510.","key":"e_1_3_2_1_3_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.5555\/647924.738755"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.5555\/553523"},{"volume-title":"University of Toronto, 2002","year":"2002","author":"Bourgeault M.","key":"e_1_3_2_1_6_1"},{"unstructured":"Cadence Virtuoso Chip Assembly Router. Datasheet available online at: http:\/\/www.cadence.com\/datasheets\/4886_virtuosoCAR_DSfnl.pdf. Cadence Virtuoso Chip Assembly Router. Datasheet available online at: http:\/\/www.cadence.com\/datasheets\/4886_virtuosoCAR_DSfnl.pdf.","key":"e_1_3_2_1_7_1"},{"unstructured":"Cadence. SKILL Programming Language http:\/\/www.cadence.com Cadence. SKILL Programming Language http:\/\/www.cadence.com","key":"e_1_3_2_1_8_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/92.784093"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1109\/43.273754"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1109\/92.475966"},{"volume-title":"University of Toronto","year":"2005","author":"Egier A.","key":"e_1_3_2_1_12_1"},{"unstructured":"J. Ferguson and A. J. Moore \"Solutions for maximizing die yield at 0.13 ?m \" Solid State Technology vol. 45 July 2002. J. Ferguson and A. J. Moore \"Solutions for maximizing die yield at 0.13 ?m \" Solid State Technology vol. 45 July 2002.","key":"e_1_3_2_1_13_1"},{"volume-title":"University of Toronto, 2002","year":"2002","author":"Fung R.","key":"e_1_3_2_1_14_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1145\/337292.337604"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1145\/611817.611820"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1126\/science.220.4598.671"},{"volume-title":"University of Toronto","year":"2004","author":"Kuon I.","key":"e_1_3_2_1_18_1"},{"key":"e_1_3_2_1_19_1","first-page":"49","volume-title":"Proceedings of the IEEE 2003 CICC","author":"Leventis P.","year":"2003"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.1145\/611817.611821"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1145\/329166.329208"},{"unstructured":"B. Nguyen O. P. Agrawal B. A. Sharpe-Giesler J. T. Wong H. M Chang and G. H. Tran. Tileable and compact layout for super variable grain blocks within FPGA device November 2000. US Patent 6 154 051. B. Nguyen O. P. Agrawal B. A. Sharpe-Giesler J. T. Wong H. M Chang and G. H. Tran. Tileable and compact layout for super variable grain blocks within FPGA device November 2000. US Patent 6 154 051.","key":"e_1_3_2_1_22_1"},{"unstructured":"LGSynth93 MCNC Benchmarks. Obtained from http:\/\/www.eecg.toronto.edu\/~lemieux\/sega\/ccts_blif.tar.gz. LGSynth93 MCNC Benchmarks. Obtained from http:\/\/www.eecg.toronto.edu\/~lemieux\/sega\/ccts_blif.tar.gz.","key":"e_1_3_2_1_23_1"},{"volume-title":"University of Toronto, 2001","year":"2001","author":"Padalia K.","key":"e_1_3_2_1_24_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_25_1","DOI":"10.1145\/611817.611842"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_26_1","DOI":"10.1145\/503048.503073"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_27_1","DOI":"10.1145\/503048.503073"},{"doi-asserted-by":"crossref","unstructured":"H. Shin C. Hu. \"Plasma-etching induced damage in thin oxide.\" In IEEE\/SEMI Advanced Semiconductor Manufacturing Conference and Workshop pp 79--83 1992. H. Shin C. Hu. \"Plasma-etching induced damage in thin oxide.\" In IEEE\/SEMI Advanced Semiconductor Manufacturing Conference and Workshop pp 79--83 1992.","key":"e_1_3_2_1_29_1","DOI":"10.1109\/ASMC.1992.253842"},{"unstructured":"Synopsys Cadabra. Product description available at: http:\/\/www.synopsys.com\/products\/ntimrg\/cadabra_ds.html. Synopsys Cadabra. Product description available at: http:\/\/www.synopsys.com\/products\/ntimrg\/cadabra_ds.html.","key":"e_1_3_2_1_30_1"},{"unstructured":"Synopsys. HSPICE frequently asked questions. http:\/\/www.synopsys.com\/products\/mixedsignal\/hspice\/hspice_faqs.html. Synopsys. HSPICE frequently asked questions. http:\/\/www.synopsys.com\/products\/mixedsignal\/hspice\/hspice_faqs.html.","key":"e_1_3_2_1_31_1"},{"unstructured":"Synopsys. Nanosim. Product Description available at: http:\/\/www.synopsys.com\/products\/mixedsignal\/nanosim\/nanosim.html. Synopsys. Nanosim. Product Description available at: http:\/\/www.synopsys.com\/products\/mixedsignal\/nanosim\/nanosim.html.","key":"e_1_3_2_1_32_1"},{"unstructured":"D. Tavana W. K. Yee and V. A. Holen. FPGA architecture with repeatable tiles including routing matrices and logic matrices October 1997. US Patent 5 682 107. D. Tavana W. K. Yee and V. A. Holen. FPGA architecture with repeatable tiles including routing matrices and logic matrices October 1997. US Patent 5 682 107.","key":"e_1_3_2_1_33_1"},{"unstructured":"Virtual Silicon Technology. Diplomat-18 standard cell library 2003. http:\/\/www.virtual-silicon.com\/. Virtual Silicon Technology. Diplomat-18 standard cell library 2003. http:\/\/www.virtual-silicon.com\/.","key":"e_1_3_2_1_34_1"},{"unstructured":"S. Wilton and J. Wu Private Communication S. Wilton and J. Wu Private Communication","key":"e_1_3_2_1_35_1"},{"unstructured":"Xilinx. FPGA Editor http:\/\/toolbox.xilinx.com\/docsan\/xilinx5\/help\/fpga_editor\/fpga_editor.htm. Xilinx. FPGA Editor http:\/\/toolbox.xilinx.com\/docsan\/xilinx5\/help\/fpga_editor\/fpga_editor.htm.","key":"e_1_3_2_1_36_1"},{"unstructured":"Xilinx. Virtex series configuration architecture user guide September 2000. XAPP151 (v1.5). Xilinx. Virtex series configuration architecture user guide September 2000. XAPP151 (v1.5).","key":"e_1_3_2_1_37_1"},{"unstructured":"Xilinx. Virtex-E 1.8v field programmable gate arrays production product specification July 2002. DS022-1 (v2.3). Xilinx. Virtex-E 1.8v field programmable gate arrays production product specification July 2002. DS022-1 (v2.3).","key":"e_1_3_2_1_38_1"}],"event":{"sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"acronym":"FPGA05","name":"FPGA05: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays 2005","location":"Monterey California USA"},"container-title":["Proceedings of the 2005 ACM\/SIGDA 13th international symposium on Field-programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1046192.1046220","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1046192.1046220","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:43:34Z","timestamp":1750286614000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1046192.1046220"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,2,20]]},"references-count":37,"alternative-id":["10.1145\/1046192.1046220","10.1145\/1046192"],"URL":"https:\/\/doi.org\/10.1145\/1046192.1046220","relation":{},"subject":[],"published":{"date-parts":[[2005,2,20]]},"assertion":[{"value":"2005-02-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}