{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:29Z","timestamp":1750308089669,"version":"3.41.0"},"reference-count":6,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2004,3,1]],"date-time":"2004-03-01T00:00:00Z","timestamp":1078099200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGMETRICS Perform. Eval. Rev."],"published-print":{"date-parts":[[2004,3]]},"abstract":"<jats:p>\n            Microprocessor research and development increasingly relies on detailed simulations to make design choices. As such, the structure, speed, and accuracy of microarchitectural simulators is of critical importance to the field. This paper describes our experiences in building two simulators, using related but distinct approaches.One of the most important attributes of a simulator is its ability to accurately convey design trends as different aspects of the microarchitecture are varied. In this work, we break down accuracy---a broad term--- into two sub-types:\n            <jats:italic>relative<\/jats:italic>\n            and\n            <jats:italic>absolute<\/jats:italic>\n            accuracy. We then discuss typical abstraction errors in power-performance simulators and show when they do (or do not) affect the design rule choices a user of those simulator might make. By performing this validation study using the Wattch and Power Timer simulators, the work addresses validation issues both broadly and in the specific case of a fairly widely-used simulator.\n          <\/jats:p>","DOI":"10.1145\/1054907.1054911","type":"journal-article","created":{"date-parts":[[2007,1,17]],"date-time":"2007-01-17T18:32:02Z","timestamp":1169058722000},"page":"13-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Power-performance simulation"],"prefix":"10.1145","volume":"31","author":[{"given":"David","family":"Brooks","sequence":"first","affiliation":[{"name":"Havard University"}]},{"given":"Pradip","family":"Bose","sequence":"additional","affiliation":[{"name":"IBM T.J. Watson Research Center"}]},{"given":"Margaret","family":"Martonosi","sequence":"additional","affiliation":[{"name":"Princeton University"}]}],"member":"320","published-online":{"date-parts":[[2004,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.823443"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_3_1","volume-title":"Power Aware Computing Systems Workshop at ASPLOS-IX","author":"Brooks D.","year":"2000","unstructured":"D. Brooks , J.-D. Wellman , P. Bose , and M. Martonosi . Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor . In Power Aware Computing Systems Workshop at ASPLOS-IX , Nov. 2000 .]] D. Brooks, J.-D. Wellman, P. Bose, and M. Martonosi. Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor. In Power Aware Computing Systems Workshop at ASPLOS-IX, Nov. 2000.]]"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/PCCC.1999.749471"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.768496"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339659"}],"container-title":["ACM SIGMETRICS Performance Evaluation Review"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1054907.1054911","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1054907.1054911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:07:53Z","timestamp":1750262873000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1054907.1054911"}},"subtitle":["design and validation strategies"],"short-title":[],"issued":{"date-parts":[[2004,3]]},"references-count":6,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2004,3]]}},"alternative-id":["10.1145\/1054907.1054911"],"URL":"https:\/\/doi.org\/10.1145\/1054907.1054911","relation":{},"ISSN":["0163-5999"],"issn-type":[{"type":"print","value":"0163-5999"}],"subject":[],"published":{"date-parts":[[2004,3]]},"assertion":[{"value":"2004-03-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}